An asynchronous pulse width modulator for DC-DC buck converter

摘要

This paper presents an asynchronous pulse width modulation (APWM) approach for the analysis of a new class of the switched mode power supply (SMPS). The proposed APWM significantly simplified the mathematical analysis by utilizing a binary comparator (BAPWM) and a distinctive delay cell instead of hysteretic comparator. By this way, the mathematical analysis can be extended to study the behavior of high-order self-oscillating modulators in terms of key parameters such as the harmonic distortion and the stability. The performance of the proposed BAPWM is deeply analyzed for different orders of loop filters (here up to third order) in both time and frequency domain. To verify the effectiveness of the proposed analytical derivations, the BAPWMs are employed in a classic synchronous DC-DC buck converter and its closed loop performance, in terms of stability, has been investigated. Then the converter is designed and simulated in 130-nm CMOS technology to convert input voltage of 5 to 3.3 V with maximum load current of 1 A, using Spectre simulator. From the post-layout simulation results, the peak efficiency conversion efficiency for 3.3 V output voltage is higher than 89%.