CAD Layout Analysis for Defect Inspection in Semiconductor Fabrication

摘要

We have been witnessing the continuous size reduction in consumer electronics devices with longer battery life. The Application Specific Integrated Circuits allow for integration of multiple electronics devices on the same dice. At the same time optimizing the transistor and device area lowers power consumption. It is a big challenge to develop such semiconductor processes and also to develop methodologies to monitor the process during semiconductor fabrication. After every major fabrication process, the wafer undergoes an inspection to detect any abnormality that may cause chip failure down the line. An optical inspection using Ultra Violet or Deep Ultra Violet light is designed to find the physical defects that might be "visible" on the wafer. In order to find electrical connection failure during fabrication, a separate approach of electron beam inspection is designed for monitoring metallization processes. In this study, we have used Computer Aided Design layout analysis to guide the defect inspection for both optical and electron beam wafer inspections. The goal was to increase the chances of finding critical defects as well as to reduce the cycle time for the inspection and defect characterization. The proposed approach has been compared with the existing baseline inspection results on the same wafer.