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Selective Check of Data-Path for Effective Fault Tolerance

机译:选择性检查数据路径的有效容错能力

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摘要

Nowadays, fault tolerance has been playing a progressively important role in covering increasing soft/hard error rates in electronic devices that accompany the advances of process technologies. Research shows that wear-out faults have a gradual onset, starting with a timing fault and then eventually leading to a permanent fault. Error detection is thus a required function to maintain execution correctness. Currently, however, many highly dependable methods to cover permanent faults are commonly over-designed by using very frequent checking, due to lack of awareness of the fault possibility in circuits used for the pending executions. In this research, to address the over-checking problem, we introduce a metric for permanent defects, as operation defective probability (ODP), to quantitatively instruct the check operations being placed only at critical positions. By using this selective checking approach, we can achieve a near-100% dependability by having about 53% less check operations, as compared to the ideal reliable method, which performs exhaustive checks to guarantee a zero-error propagation. By this means, we are able to reduce 21.7% power consumption by avoiding the non-critical checking inside the over-designed approach.
机译:如今,随着过程技术的发展,容错在覆盖电子设备中不断增加的软/硬错误率方面一直扮演着越来越重要的角色。研究表明,磨损故障是逐渐发生的,从定时故障开始,然后最终导致永久性故障。因此,错误检测是维持执行正确性所必需的功能。然而,由于缺乏对用于待决执行的电路中的故障可能性的认识,当前,许多用于覆盖永久性故障的高度可靠的方法通常通过使用非常频繁的检查而被过度设计。在这项研究中,为了解决过度检查的问题,我们引入了永久性缺陷的度量标准,称为操作缺陷概率(ODP),以定量指示仅在关键位置进行的检查操作。通过使用这种选择性检查方法,与理想的可靠方法(执行详尽的检查以确保零错误传播)相比,我们可以通过减少约53%的检查操作来实现接近100%的可靠性。通过这种方式,我们可以避免过度设计的方法中的非关键检查,从而降低21.7%的功耗。

著录项

  • 来源
    《IEICE Transactions on Information and Systems》 |2013年第8期|1592-1601|共10页
  • 作者单位

    Graduate School of Information Science, Nara Institute of Science and Technology, Ikoma-shi, 630-0192 Japan;

    Graduate School of Information Science, Nara Institute of Science and Technology, Ikoma-shi, 630-0192 Japan;

    Graduate School of Information Science, Nara Institute of Science and Technology, Ikoma-shi, 630-0192 Japan;

    College of Information Science and Engineering, Ritsumeikan University, Kusatsu-shi, 525-8577 Japan;

    Graduate School of Information Science, Nara Institute of Science and Technology, Ikoma-shi, 630-0192 Japan;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    low power; fault-tolerant computing; FU array;

    机译:低电量;容错计算;FU阵列;

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