Parasitic extraction methodology for insulated gate bipolartransistors

摘要

This paper presents a methodology for extraction of the electricalnpackage parasitics of insulated gate bipolar transistor power modulesnusing simple electrical measurements. Non-idealities of devicenperformance in zero-voltage and zero-current switching are exploited tonobtain the parasitic collector and emitter inductance. Simple impedancenmeasurements are performed to extract gate inductance and resistance.nThe extraction methodology is validated by comparing two-dimensionalnnumerical simulation results including package parasitics with measuredndata. A close match between the two indicates the robustness of thenextraction procedure