Low-Power Neuromorphic Hardware for Signal Processing Applications: A Review of Architectural and System-Level Design Approaches

Rajendran Bipin; Sebastian Abu; Schmuker Michael; Srinivasa Narayan; Eleftheriou Evangelos

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Low-Power Neuromorphic Hardware for Signal Processing Applications: A Review of Architectural and System-Level Design Approaches

机译：用于信号处理应用的低功耗神经形态硬件：体系结构和系统级设计方法的回顾

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来源
《IEEE Signal Processing Magazine》 |2019年第6期|97-110|共14页
作者
Rajendran Bipin; Sebastian Abu; Schmuker Michael; Srinivasa Narayan; Eleftheriou Evangelos;
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作者单位

New Jersey Inst Technol Elect & Comp Engn Newark NJ 07102 USA|IBM Corp TJ Watson Res Ctr Yorktown Hts NY USA|Indian Inst Technol Dept Elect Engn Mumbai Maharashtra India;

IBM Res Zurich Zurich Switzerland;

Univ Hertfordshire Dept Comp Sci Hatfield Herts England|Univ Sussex Falmer England|Univ Hertfordshire Hatfield Herts England;

Univ Illinois Beckman Inst Human Comp Intelligent Interact Grp Champaign IL USA|Intel Labs Machine Intelligence Res Programs Santa Clara CA USA|Eta Compute Westlake Village CA USA;

IBM Res Zurich Zurich Switzerland|IEEE Piscataway NJ USA;

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1. Designing BEE: A Hardware Emulation Engine for Signal Processing in Low-Power Wireless Applications [J] . Kimmo Kuusilinna, Chen Chang, M. Josephine Ammer, EURASIP journal on advances in signal processing . 2003,第6期

机译：设计BEE：用于低功耗无线应用中信号处理的硬件仿真引擎
2. Designing BEE: A Hardware Emulation Engine for Signal Processing in Low-Power Wireless Applications [J] . Kimmo Kuusilinna, Chen Chang, M. Josephine Ammer, EURASIP journal on applied signal processing . 2002,第6期

机译：设计BEE：用于低功耗无线应用中信号处理的硬件仿真引擎
3. ECG Authentication Hardware Design With Low-Power Signal Processing and Neural Network Optimization With Low Precision and Structured Compression [J] . Cherupally Sai Kiran, Yin Shihui, Kadetotad Deepak, IEEE transactions on biomedical circuits and systems . 2020,第2期

机译：ECG认证硬件设计具有低功耗信号处理和神经网络优化，具有低精度和结构压缩
4. Emerging neuromorphic computing architectures enabling hardware for cognitive information processing applications [C] . Pino Robinson E., Genello Gerard, Bishop Morgan, 2010 2nd International Workshop on Cognitive Information Processing . 2010

机译：新兴的神经形态计算架构和支持硬件的认知信息处理应用程序
5. Algorithmic and architectural low-power techniques for digital signal processing and wireless communication applications. [D] . Wang, Yongtao. 2005

机译：用于数字信号处理和无线通信应用的算法和体系结构低功耗技术。
6. HFNet: A CNN Architecture Co-designed for Neuromorphic Hardware With a Crossbar Array of Synapses [O] . Roshan Gopalakrishnan, Yansong Chua, Pengfei Sun, 2020

机译：HFNET：CNN架构共同设计用于具有横杆突触阵列的神经形态硬件
7. Design of hardware architectures for HMM–based signal processing systems with applications to advanced human-machine interfaces [O] . Malatesta Alessandro 2009

机译：基于HMM的信号处理系统的硬件体系结构设计，并应用于高级人机界面
8. Emerging Neuromorphic Computing Architectures & Enabling Hardware for Cognitive Information Processing Applications [R] . Pino, R. E., Genello, G., Bishop, M., 2010

机译：新兴的神经形态计算架构和用于认知信息处理应用的硬件

Low-Power Neuromorphic Hardware for Signal Processing Applications: A Review of Architectural and System-Level Design Approaches

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