Optimisation of high-performance gates in AlGaAs/GaAs quantum-welltechnology

摘要

Ultra-high-speed logic gates are proposed using heterostructurenfield-effect transistors. A simple noise margin optimisation method isnapplied to improve the performance in terms of noise margin and delay. An16-bit binary carry look-ahead adder is then used as a demonstratorncircuit to show the advantages of the logic gates over the standardndirect coupled FET logic implementation