Design and characterisation of a CMOS VLSI self-timed multiplierarchitecture based on a bit-level pipelined-array structure

摘要

The authors describe the design, integration and characterisationnof a bit-level pipelined self-timed multiplier architecture. Thendifferential structure SODS (switched-output differential structure) hasnbeen used for computation blocks and the PLCAR structure (protocol andnlatching controlled by acknowledge and request) for the interfacenblocks, introduced in an array-based architecture. A 4×4-bitnmultiplier has been integrated in a 1.0 Μm CMOS technology and thenproposed architecture has been compared with other asynchronousnapproaches, showing a considerable improvement, up to 50%, in terms ofnarea, speed and power consumption. Compared with a synchronous approach,nthe main advantage of the proposed architecture is a lower powernconsumption below a certain incoming input data rate, but at the expensenof area and speed