Multi-level factorisation technique for pass transistor logic

摘要

Discusses a technique of using multi-level logic synthesis tondesign pass transistor logic (PTL) based on algebraic factorisation.nTechniques already applied to conventional AND-OR type networks arenshown to be not useful for factorisation of PTL networks. Starting withnthe set of all prime pass implicants, the steps of selecting a cover andnfactorising a function, using a greedy heuristic, are combined. Fromnmany examples using MCNC benchmark circuits, the algorithm achieves anconsiderable improvement (an average of 14% and up to 50% savings) overnPTL circuits obtained from conventional two-level design methods