Variable sampling window flip-flops for low-power high-speed VLSI

摘要

The authors describe novel flip-flops with improved robustness and reduced power consumption. The variable sampling window flip-flop (VSWFF) adjusts the width of the sampling window according to input data, providing robust data latching as well as shorter hold time. The flip-flop also reduces internal power consumption for high input switching activities. The clock swing-reduced variable sampling window flip-flop (CSR-VSWFF) reduces clock power consumption by allowing the use of a small swing clock. Unlike conventional reduced clock swing flip-flops, the proposed designs require no additional voltage higher than the supply voltage, eliminating the design overhead related to the generation and distribution of this voltage. Simulation results indicate that the proposed flip-flops provide uniform latency for a narrower sampling window and reduced power-delay product compared to conventional flip-flops. To evaluate the performance of the proposed flip-flops, test structures were designed and implemented in 0.35 (mu)m CMOS process technology. Experimental results indicate that the VSWFF consumes less power under conditions of maximum input switching activity. A synchronous counter designed using the CSR-VSWFF provides improved performance in terms of power consumption with no use of an extra voltage higher than the supply voltage.