- - - LOW-POWER SMALL-AREA HIGH-SPEED MASTER-SLAVE FLIP-FLOP CIRCUIT AND DEVICES HAVING THE SAME

摘要

In an integrated circuit comprising positive edge triggered master-slave flip-flop circuits each sharing one clock signal input node that receives a clock signal, said positive edge triggered master-slave flip-flop circuit any one of them is a first time to generate an inverted clock signal transitioning from the high level to the low level at a second time point later than the first time point by delaying the clock signal transitioning from the low level to the high level at a first time point an input stage including a first inversion circuit, a transfer gate including a first PMOS transistor and a first NMOS transistor, a second PMOS transistor and a second NMOS transistor, the input stage including an input terminal for receiving an input signal, and an output terminal of the input stage and a second inverting circuit connected between an input terminal of the transfer gate, wherein the clock signal is supplied to the gate of the first NMOS transistor of the transfer gate and the second PMOS transistor of the input stage, the inverted clock signal is supplied to the gate of the first PMOS transistor of the transfer gate and is supplied to the second NMOS transistor of the input stage.