Efficient and flexible architecture for AES

摘要

A new flexible AES architecture is proposed that can perform both encryption and decryption with 128-, 192-, and 256-bit key options by a novel on-the-fly key generation module. The corresponding subkeys for encryption and decryption are generated concurrently as the appropriate configuration parameters (signals) are set. The proposed design operates in CBCk (cipher block chain) mode and processes three blocks of data simultaneously. The architecture is simulated in Verilog HDL and implemented in FPGA and ASIC designs. The performance comparison indicates that the design has high throughput and small circuit area