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首页> 外文期刊>Emerging and Selected Topics in Power Electronics, IEEE Journal of >1.2-kV 4H-SiC Merged PiN Schottky Diode With Improved Surge Current Capability
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1.2-kV 4H-SiC Merged PiN Schottky Diode With Improved Surge Current Capability

机译:具有改善的浪涌电流能力的1.2kV 4H-SiC合并式PiN肖特基二极管

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摘要

This paper presents the design and experimental analysis of 1200-V 4H-silicon carbide (SiC) merged PiN Schottky (MPS) diodes. Design considerations and device performances of the MPS diodes are compared with those of the junction barrier Schottky (JBS) diodes via numerical simulation and experiments. Due to the limited P+ width/ratio in JBS diodes, p-n junction is not turned on until very high current/voltage bias is applied. This increases the device voltage drop and energy dissipation in high current stress conditions. Thanks to the wide P+ region design and the ohmic contact on the P+ regions, the p-n junction turn-on voltage in MPS diodes is substantially decreased, and the surge current capability is improved accordingly. Furthermore, the surge capability of two layouts of the MPS diodes are compared. Layout A with similar to 60% high P+ ratio can improve the surge current capability by 10% and 20% compared with layout B design (with similar to 50% P+ ratio) and pure JBS diode (with similar to 40% P+ ratio), respectively. The reliability of the MPS diodes is studied by repetitive pulse surge current tests. No obvious degradation appears after 5500 test cycles under a surge current stress 20 times the device nominal current rating.
机译:本文介绍了1200V 4H碳化硅(SiC)合并的PiN肖特基(MPS)二极管的设计和实验分析。通过数值模拟和实验,将MPS二极管的设计考虑因素和器件性能与结势垒肖特基(JBS)二极管的设计考虑因素和器件性能进行了比较。由于JBS二极管的P +宽度/比率有限,因此在施加非常高的电流/电压偏置之前,p-n结不会打开。在高电流应力条件下,这会增加器件的压降和能量耗散。由于宽的P +区域设计和P +区域上的欧姆接触,MPS二极管中的p-n结导通电压大大降低,浪涌电流能力也相应提高。此外,比较了两种布局的MPS二极管的浪涌能力。与布局B设计(P +比率接近50%)和纯JBS二极管(P +比率接近40%)相比,布局A的P +比率接近60%的浪涌电流能力可以提高10%和20%,分别。通过重复脉冲浪涌电流测试研究了MPS二极管的可靠性。在5500个测试周期后,在浪涌电流应力为器件额定电流额定值20倍的情况下,没有出现明显的劣化。

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