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首页> 外文期刊>IEEE Electron Device Letters >Co-Optimization of the Metal Gate/High-k Stack to Achieve High-Field Mobility >90% of SiO{sub}2 Universal Mobility With an EOT= ~ 1 nm
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Co-Optimization of the Metal Gate/High-k Stack to Achieve High-Field Mobility >90% of SiO{sub}2 Universal Mobility With an EOT= ~ 1 nm

机译:共同优化金属栅极/高k堆栈,以实现EOT =〜1 nm的高90%SiO {sub} 2通用迁移率的高场迁移率

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摘要

HfO{sub}2 and HfSiON gate dielectrics with high-field electron mobility greater than 90% of the SiO{sub}2 universal mobility and equivalent oxide thickness (EOT) approaching 1 nm are successfully achieved by co-optimizing the metal gate/high-k/bottom interface stack. Besides the thickness of the high-k dielectrics, the thickness of the ALD TiN metal gate and the formation of the bottom interface also play an important role in scaling EOT and achieving high electron mobility. A phase transformation is observed for aggressively scaled HfO{sub}2 and HfSiON, which may be responsible for the high mobility and low charge trapping of the optimized HfO{sub}2 gate stack.
机译:通过共同优化金属栅极/高电子,成功实现了高场电子迁移率大于SiO {sub} 2通用迁移率的90%的HfO {sub} 2和HfSiON栅极电介质,等效氧化物厚度(EOT)接近1 nm。 -k /底部接口堆栈。除了高k电介质的厚度之外,ALD TiN金属栅极的厚度和底部界面的形成在缩放EOT和实现高电子迁移率方面也起着重要作用。观察到大规模缩放的HfO {sub} 2和HfSiON的相变,这可能是优化的HfO {sub} 2栅堆叠的高迁移率和低电荷俘获的原因。

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