How clear is your crystal ball?

摘要

Retend, for a moment, that you're an Intel product architect responsible for defining the company's next-generation microprocessor family. You know that if you lengthen the CPU's pipeline, you'll be able to crank up the chip's core-clock frequency, pleasing consumers that pick their PCs using only a simplistic "more-megahertz-are-better" stratagem. You also know that emerging multimedia-centric applications, thanks to their predictable code- and data-access patterns, are compatible with deep pipelines and will benefit from this higher speed. But traditional, "office" applications, such as e-mail, spreadsheets, Web browsing, and word processing, are less pipeline-friendly. Despite your best efforts at beefing up on-chip cache and branch-prediction logic and minimizing the performance impact of a branch misprediction, these bread-and-butter applications will likely run slower on a deep-pipeline device than a shallow-pipeline alternative at the same clock frequency. What do you do?