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Research and Design of AES Security Processor Model Based on FPGA

机译:基于FPGA的AES安全处理器模型的研究与设计。

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The rapid development of information technology and how to ensure the safe transmission of information have always been a hot topic in the field of computer security. AES is the most mainstream and common encryption standard in the 21st century, with the advantages of high efficiency, good stability and flexibility.Taking information encryption as the background and FPGA design as the foundation, this paper realizes the security processor model based on advanced encryption algorithm AES, and to improve the way of collaboration between modules, especially encryption module and key extension module, making full use of the parallel and water technology to enhance the system run speed, through the design of the hardware that allows the encryption system to achieve more efficient and more stable level of security. The system has the advantages of simple circuit structure and low occupancy resources so it can be very practical.
机译:信息技术的飞速发展以及如何确保信息的安全传输一直是计算机安全领域的热门话题。 AES是21世纪最主流,最通用的加密标准,具有效率高,稳定性好,灵活性高的特点。本文以信息加密为背景,以FPGA设计为基础,实现了基于高级加密的安全处理器模型。算法AES,并改善模块之间(尤其是加密模块和密钥扩展模块)之间的协作方式,充分利用并行和水技术,通过允许加密系统实现的硬件设计来提高系统运行速度更高效,更稳定的安全级别。该系统具有电路结构简单,占用资源少的优点,非常实用。

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