An Optimization Design Strategy for Arithmetic Logic Unit

摘要

The work in this paper presents a step by step optimization approach for the Arithmetic Logic Unit (ALU) at the logic circuit level. Herein concept of resource sharing (viz. operator sharing, functionality sharing), the concept of optimized arithmetic expressions (viz. arranging expression trees for minimum delay, sharing common subexpression, merging cascaded adders with carry) for optimization of combinational blocks in ALU had been used. The work in this paper shows how a simple tools like Deeds Digital Circuit Simulator (open source) or Aldec's Active HDL in combination with synthesis tool which can be used as effective teaching resource to teach concept of digital circuit design and thereby provides a vision to beginners how to start with VLSI project in VLSI digital domain and make it to a successful end.