High level modeling of Dynamic Reconfigurable FPGAs

摘要

As System-on-Chip (SoC) based embedded systemshave become a defacto industry standard, their overall designcomplexity has increased exponentially in recent years,necessitating the introduction of new seamless methodologiesand tools to handle the SoC codesign aspects. This paperpresents a novel SoC co-design methodology based on ModelDriven Engineering and the Modeling and Analysisof Real-Time and Embedded Systems (MARTE) standard, permitting usto raise the abstraction levels and allows to model fine grainreconfigurable architectures such as FPGAs. Extensions of thismethodology have enabled us to integrate new features such asPartial Dynamic Reconfiguration supported by Modern FPGAs.The overall objective is to carry out system modeling at a highabstraction level expressed in a graphical language like Unified Modeling Language (UML) and afterwards transformationof these models automatically generate the necessary code forFPGA synthesis.