We present a method for implementing high speed finite impulseresponse (FIR) filters on field programmable gate arrays (FPGAs). Our algorithm is a multiplierless technique where fixedcoefficient multipliers are replaced with a series of add andshift operations. The first phase of our algorithm uses registeredadders and hardwired shifts. Here, a modified common subexpressionelimination (CSE) algorithm reduces the number of adders whilemaintaining performance. The second phase optimizes routing delayusing prelayout wire length estimation techniques to improve thefinal placed and routed design. The optimization target platformsare Xilinx Virtex FPGA devices where we compare the implementationresults with those produced by Xilinx Coregen, which is based ondistributed arithmetic (DA). We observed up to 50% reductionin the number of slices and up to 75% reduction in the numberof look up tables (LUTs) for fully parallel implementationscompared to DA method. Also, there is 50% reduction in thetotal dynamic power consumption of the filters. Our designsperform up to 27% faster than the multiply accumulate (MAC)filters implemented by Xilinx Coregen tool using DSP blocks. Forplacement, there is a saving up to 20% in number of routingchannels. This results in lower congestion and up to 8%reduction in average wirelength.
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