Design and Verification of AMBA AHBLite protocol using Verilog HDL

摘要

The SOC plan confronts a crevice between generation limit and time to market weights. The outline space develops with changes underway limits as far as measure of time to plan a framework utilizing these abilities. On one hand, shorter product life cycles are forcing an aggressive reduction of the time-to-market, fast simulation capabilities are required for coping with the immense design space that is to be explored; these are specially needed during early stages of the design. This need has driven the improvement of exchange level models, which are theoretical models that have been designed to run much quicker than synthesizable models.The pressure for faster executing models extends especially to the frequently reused communication libraries. AMBA AHB-Lite addresses the requirements of high-performance synthesizable designs. It is a transport interface that provides support to a solitary transport ace and gives elite data transfer capacity.This paper describes the system level modelling of the Advanced HighperformanceBus Lite (AHB-Lite) subset of AHB which is a part of the Advanced Microprocessor Bus Architecture(AMBA). It also includes the design and verification ofAHB-Lite protocol for sequentialand non-sequential (increment and wrap of differentburst sizes) transfers.