Low Cost Network on Chip Router Design for Torus Topology

摘要

Network on chip (NoC) has emerged as a good solution to enhance the communication structures for complex System on Chip (SoC). Unlike bus based system, NoC integrate hundreds or thousands of intellectual properties (IPs) like processors, memories or other custom design on a single chip. This work aims at providing comparison and performance analysis of NoC router. The proposal supports the torus topology and implements the negative-first routing algorithm to avoid deadlocks. We describe the router architecture which composed of the input module, the switch allocator and the crossbar traversal. Results are presented and compared with other works in terms of maximal clock frequency, area, power consumption and peak performance.