机译:FPGA中浮点加法器的设计折衷分析
Department of Electrical and Computer Engineering, University of Saskatchewan, 57 Campus Drive, Saskatoon, Saskatchewan S7N 5A9, Canada;
Department of Electrical and Computer Engineering, University of Saskatchewan, 57 Campus Drive, Saskatoon, Saskatchewan S7N 5A9, Canada;
Department of Electrical and Computer Engineering, University of Saskatchewan, 57 Campus Drive, Saskatoon, Saskatchewan S7N 5A9, Canada;
Department of Electronics and Information Engineering, Chonbuk National University, 664-14 1 Ga Deokjin-Dong, Jeonju-City, Jeonbuk, South Korea 561-756;
Department of Electrical and Computer Engineering, University of Saskatchewan, 57 Campus Drive, Saskatoon, Saskatchewan S7N 5A9, Canada;
机译:FPGA中浮点加法器的设计折衷分析
机译:FPGA的快速,高效浮点加法器和乘法器
机译:不精确浮点加法器的设计与分析
机译:浮点超越函数的FPGA设计折衷
机译:浮点FPGA加法器/减法器和乘法器的实现。
机译:基于模型的设计浮点累加器。研究案例:支持向量机内核功能的FPGA实现
机译:算术运营商浮点库的FPGA设计权衡
机译:FpGa上基于浮点的应用的面积和功耗性能分析