CNFET-Based Design of Energy-Efficient Symmetric Three-Input XOR and Full Adder Circuits

摘要

This paper presents a novel CNFET-based design for three-input Exclusive-OR circuits as well as Full Adder cells for low-voltage and high frequency applications. These designs take advantage of high performance and low power consumption and have simple and symmetric structures. Comprehensive experiments are carried out to evaluate the performance of the proposed designs in various conditions. Simulations are performed using Synopsys HSPICE with 32 nm CMOS and 32 nm CNFET technologies. The simulation results demonstrate the superiority of the proposed structures in terms of speed, power consumption, and power-delay-product compared to other modern CMOS and CNFET-based Full Adder cells.