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International Conference on VLSI Design;International Conference on Embedded Systems Design
International Conference on VLSI Design;International Conference on Embedded Systems Design
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1.
Invited Talk: IoT Protocols War and the Way Forward
机译:
特邀演讲:物联网协议之战与未来之路
作者:
Gupta V.
;
Jayaraghavendran
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
Internet of Things;
transport protocols;
6lowPAN;
AMQP;
AllJoyn framework;
Bluetooth;
CoAP;
DNP3;
HTTPasRESTful API;
IPv6;
Internet of Things;
IoT landscape;
IoT protocols;
M2M;
MQTT;
UPnP;
Web transfer protocol;
Wifi;
XMPP;
Zigbee standards;
constrained nodes;
ecosystem;
lossy networks;
low power networks;
machine to machine communication;
queuing system;
servers;
technological revolution;
Business;
Internet of things;
Magnetic heads;
Protocols;
Servers;
Telecommunications;
Very large scale integration;
2.
Tutorial T8: Scheduling Issues in Embedded Real-Time Systems
机译:
教程T8:嵌入式实时系统中的调度问题
作者:
Ramanathan P.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
embedded systems;
multiprocessing systems;
processor scheduling;
embedded real-time system;
multicore system;
processor power;
scheduling algorithm;
thermal constraint;
Integrated circuit modeling;
Real-time systems;
Tutorials;
Very large scale integration;
3.
Embedded Tutorial ET2: Volume Diagnosis for Yield Improvement
机译:
嵌入式教程ET2:提高产量的体积诊断
作者:
Wu-Tung Cheng
;
Reddy S.M.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
VLSI;
data mining;
failure analysis;
learning (artificial intelligence);
statistical analysis;
VLSI devices;
data mining;
defect distribution;
machine learning;
statistical technique;
subnanometer technologies;
volume diagnosis;
yield improvement;
Educational institutions;
Failure analysis;
Manufacturing processes;
Object recognition;
Systematics;
Transistors;
Very large scale integration;
4.
Tutorial T2: Validation and Debug of Security and Trust Issues in Embedded Systems
机译:
教程T2:嵌入式系统中安全性和信任问题的验证和调试
作者:
Mishra P.
;
Bhunia S.
;
Ravi S.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
computer debugging;
embedded systems;
industrial property;
security of data;
system-on-chip;
SoC computing platforms;
debug flow;
embedded systems;
formal methods;
hardware IP;
reusable hardware intellectual property;
security attacks;
security failures;
security validation;
security vulnerabilities;
system-on-chip;
trust validation;
Awards activities;
Design automation;
Hardware;
Security;
System-on-chip;
Tutorials;
Very large scale integration;
5.
Tutorial T7: Physically Unclonable Function: A Promising Security Primitive for Internet of Things
机译:
教程T7:物理上不可克隆的功能:物联网的有希望的安全性原语
作者:
Mukhopadhyay D.
;
Chakraborty R.S.
;
Phuong Ha Nguyen
;
Sahoo D.P.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
Internet of Things;
computer crime;
computer network security;
cryptographic protocols;
learning (artificial intelligence);
message authentication;
Internet of Things;
IoT;
PUF circuit;
PUF fundamentals;
PUF-based authentication protocols;
cryptographic algorithms;
defence strategies;
hardware security primitives;
intelligent attacks;
intercommunicating smart devices;
lightweight PUF designs;
lightweight authentication protocols;
machine learning;
physical attacks;
physically unclonable functions;
resource constrained smart devices;
secret key;
security analysis;
security applications;
security protocols;
side-channel analysis;
side-channel attack;
Computer science;
Cryptography;
Hardware;
Patents;
Tutorials;
6.
A Frequency Scan Scheme for PLL-Based Locking to High-Q MEMS Resonators
机译:
一种基于PLL的高Q MEMS谐振器锁定频率扫描方案
作者:
Kumar A.
;
Dikshit A.
;
Clark B.
;
Yan J.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
Q-factor;
band-pass filters;
charge pump circuits;
comparators (circuits);
gyroscopes;
microcavities;
micromechanical resonators;
phase locked loops;
reliability;
AC hysteresis;
ADXRS290 gyroscope product;
DC hysteresis;
PLL lock reliability;
PLL-based locking;
TSMC micron process;
charge pump-based PLL;
comparator circuit;
feedback loop;
frequency scan scheme;
frequency scan technique;
high-Q MEMS resonators;
in-built band pass filter;
input sinusoid;
natural frequency oscillation;
quality factor;
resonator loop;
signal level;
size 0.18 mum;
startup time;
vibratory gyroscopes;
Clocks;
Gyroscopes;
Optical resonators;
Oscillators;
Phase locked loops;
Resonant frequency;
Resonator filters;
Micro-electromechanical (MEMS) resonator;
PLL;
drive loop;
frequency scan;
resonance tracking;
7.
A Novel Ternary Content-Addressable Memory (TCAM) Design Using Reversible Logic
机译:
使用可逆逻辑的新型三元内容可寻址存储器(TCAM)设计
作者:
Kumar S.D.
;
Sk N.M.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
content-addressable storage;
logic design;
power consumption;
TCAM cells;
garbage outputs;
lookup table function;
packet data transfers;
packet forwarding;
power consumption;
quantum cost;
reversible logic;
ternary content-addressable memory;
Arrays;
Computer aided manufacturing;
Delays;
Heating;
Logic gates;
SRAM cells;
Content addressable memory;
Garbage output;
Power consumption;
Quantum cost;
Reversible logic;
TCAM;
8.
A CMOS 90nm 50Mhz Supply Noise Tolerant High Density 8T-NAND ROM
机译:
CMOS 90nm 50Mhz电源噪声容忍高密度8T-NAND ROM
作者:
Dhori K.J.
;
Kumar V.
;
Kumar A.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
CMOS memory circuits;
NAND circuits;
logic design;
low-power electronics;
read-only storage;
decoupling capacitor;
frequency 50 MHz;
high peak current;
inductive reactance;
noise tolerant high density 8T-NAND ROM;
noise tolerant reference generation;
on-chip power grid design;
power supply noise;
read failure;
read only memory;
size 90 nm;
Capacitance;
Computer architecture;
Discharges (electric);
Fluctuations;
Noise;
Read only memory;
Sensors;
low power;
read only memories;
single ended sense amplifier;
supply noise;
9.
A Novel CKE-ODT-CSN Encoding Scheme in DDR Memory Interface
机译:
DDR存储器接口中的新型CKE-ODT-CSN编码方案
作者:
Murugan V.I.
;
Mayandi N.
;
Arul S.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
DRAM chips;
encoding;
CKE-ODT-CSN encoding;
DDR memory interface;
DRAM;
clock enable-on die termination-chip select encoding;
coding algorithm;
double data rate DDR CA topology;
pin elimination;
single data rate DDR CA topology;
Clocks;
Decoding;
Delays;
Encoding;
Pins;
Random access memory;
Topology;
Chip Select (CSN);
Clock Enable (CKE);
DDR memory;
On Die Termination (ODT);
pin-elimination;
10.
A Wide Tuning Range LC Quadrature Phase Oscillator Employing Mode Switching
机译:
采用模式切换的宽调谐范围LC正交相位振荡器
作者:
Rudrapati S.
;
Jagtap S.
;
Shaikh M.U.
;
Gupta S.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
CMOS integrated circuits;
circuit simulation;
microwave oscillators;
varactors;
CMOS technology;
LC quadrature phase oscillator;
LC tanks;
circuit simulation;
frequency 11 GHz;
mode switching;
parallel coupling;
parallel-coupled topology;
series-coupled topology;
size 90 nm;
varactors;
wide tuning range;
Capacitors;
Couplings;
Oscillators;
Quality of service;
Transconductance;
Transistors;
Tuning;
LC oscillators;
Quadrature phase oscillators;
modes of quadrature phase oscillators;
parallel coupling;
phase noise;
series coupling;
11.
On Slew Rate Enhancement in Class-A Opamps Using Local Common-Mode Feedback
机译:
利用本地共模反馈提高A类运算放大器的摆率
作者:
Rakshitdatta K.S.
;
Krishnapura N.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
operational amplifiers;
class-AB output stage;
local common-mode feedback loop;
multistage fully-differential opamp;
output common-mode voltage;
single-common-mode feedback loop;
slew rate enhancement;
two-stage Miller-compensated class-A opamp;
Capacitors;
Detectors;
Feedback loop;
Integrated circuits;
Logic gates;
Switches;
Transistors;
amplifiers;
common-mode feedback;
slew rate enhancement;
12.
RELSPEC: A Framework for Early Reliability Refinement of Embedded Applications
机译:
RELSPEC:嵌入式应用程序早期可靠性优化的框架
作者:
Ghosh S.K.
;
Hazra A.
;
Dey S.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
automotive engineering;
embedded systems;
probability;
safety-critical software;
software reliability;
RELSPEC;
automatically constructed intermediate probabilistic models;
automotive case-studies;
design flow;
early reliability refinement;
safety-critical embedded application;
Analytical models;
Computational modeling;
Markov processes;
Probabilistic logic;
Reliability engineering;
Standards;
Embedded Systems;
Reliability;
Specification;
13.
A Flexible Scalable Hardware Architecture for Radial Basis Function Neural Networks
机译:
径向基函数神经网络的灵活可扩展硬件体系结构
作者:
Mohammadi M.
;
Satpute N.
;
Ronge R.
;
Chandiramani J.R.
;
Nandy S.K.
;
Raihan A.
;
Verma T.
;
Narayan R.
;
Bhattacharya S.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
Gaussian processes;
learning (artificial intelligence);
multiprocessing systems;
pattern clustering;
radial basis function networks;
time series;
FPGA;
Gaussian function;
RBFNN;
center learning;
flexible scalable hardware architecture;
hybrid structure;
hyper cells;
k-means clustering method;
multiprocessor system;
nonlinear identification;
offline training;
online training;
pattern recognition;
pseudo inverse;
radial basis function neural networks;
soft core processor;
time series prediction;
Clocks;
Computer architecture;
Euclidean distance;
Generators;
Hardware;
Neurons;
Training;
Multi Processor System on Chip;
Pattern Recognition;
Radial Basis Function Neural Network;
Reconfigurable Architecture;
14.
A Hardware and Thermal Analysis of DVFS in a Multi-core System with Hybrid WNoC Architecture
机译:
混合WNoC架构的多核系统中DVFS的硬件和热分析
作者:
Gade S.H.
;
Mondal H.K.
;
Deb S.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
CMOS integrated circuits;
low-power electronics;
multifrequency antennas;
multiprocessing systems;
network-on-chip;
radio transceivers;
thermal analysis;
CMOS manufacturing technologies;
DVFS;
SoC;
centralized controller;
dual band antenna;
dual band transceiver;
dynamic voltage-frequency scaling;
hardware analysis;
hybrid WNoC architecture;
many core;
multicore systems;
power consumption;
power density;
signal transmission;
system-on-chip;
thermal analysis;
wireless interfaces;
Antennas;
Benchmark testing;
Dual band;
Hardware;
System-on-chip;
Transceivers;
Wireless communication;
dual band;
dynamic voltage/frequency scaling;
low power;
thermal analysis;
wireless;
15.
A 300 KBPS 23.2 MHz Binary Frequency Shift Keying Transmitter for USB Power Line Communication in 180 nm BiCMOS
机译:
用于180 nm BiCMOS中USB电力线通信的300 KBPS 23.2 MHz二进制频移键控发射机
作者:
Rao A.S.
;
Subburaj K.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
BiCMOS integrated circuits;
carrier transmission on power lines;
digital-analogue conversion;
frequency shift keying;
impedance matching;
phase locked loops;
radio transmitters;
signal generators;
BiCMOS measurement;
USB power delivery standard;
USB power line communication;
binary frequency shift keying transmitter;
bit rate 300 kbit/s;
digital clock rate converter;
direct digital synthesis;
frequency 23.2 kHz;
impedance matching;
intelligent frequency planning;
power line network;
signal generation;
sine-weighted DAC;
size 180 nm;
unmodulated high frequency PLL;
Clocks;
Frequency conversion;
Frequency shift keying;
Harmonic analysis;
Phase locked loops;
Transmitters;
Frequency shift keying transmitters;
direct digital synthesis;
driver circuit;
power amplifier;
power line communication;
16.
A Methodology for Placement of Regular and Structured Circuits
机译:
规则电路和结构化电路的放置方法
作者:
Chatterjee S.
;
Saun V.S.
;
Arunachalam A.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
circuit optimisation;
clocks;
logic circuits;
logic design;
bit slice structure;
bit slice tiling;
bit-sliced pattern;
bit-sliced structure intact;
clock pins;
data path circuits;
data path elements;
nanometer nodes;
on control pins;
optimization tricks;
quality of results;
random logic;
route tool;
separate data path placer;
straight routes;
structured circuits;
Algorithm design and analysis;
Law;
Manuals;
Optimization;
Pins;
Routing;
Bit Slice Pattern;
Datapath;
Tiling;
17.
FirmLeak: A Framework for Efficient and Accurate Runtime Estimation of Leakage Power by Firmware
机译:
FirmLeak:一种通过固件高效准确地估计泄漏功率的框架
作者:
Joseph A.
;
Haridass A.
;
Lefurgy C.
;
Rachamalla S.
;
Pai S.
;
Chinnakkonda D.
;
Goyal V.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
firmware;
microprocessor chips;
power aware computing;
power consumption;
FirmLeak;
POWER7+ microprocessor;
cloud computing;
dynamic power components;
fan power consumption;
firmware;
leakage power components;
manufacturing variation;
microprocessor leakage power;
optimizations;
per-core voltage domains;
power-gating regions;
real-time estimation;
runtime estimation;
system software;
total microprocessor power;
Abstracts;
Estimation;
Hardware;
Microprocessors;
Microprogramming;
Power demand;
Runtime;
18.
A High-Efficiency Switched-Capacitance HTFET Charge Pump for Low-Input-Voltage Applications
机译:
用于低输入电压应用的高效开关电容HTFET电荷泵
作者:
Unsuk Heo
;
Xueqing Li
;
Huichu Liu
;
Gupta Sumeet
;
Datta Suman
;
Narayanan Vijaykrishnan
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
III-V semiconductors;
charge pump circuits;
field effect transistors;
low-power electronics;
switched capacitor networks;
tunnel transistors;
III-V HTFET technology;
PCE;
cross-coupled charge pump topology;
efficiency 90.4 percent;
efficiency 91.4 percent;
heterojunction tunnel field-effect transistor;
low-input-voltage applications;
power-conversion-efficiency;
resistance 1 kohm;
size 20 nm;
switched-capacitance charge pump;
uni-directional current conduction;
voltage 0.20 V to 0.57 V;
Capacitors;
Charge pumps;
Energy loss;
Integrated circuit modeling;
Phase control;
Silicon;
Topology;
Charge pump;
DC-DC converter;
power-conversion-efficiency (PCE);
switched-capacitance;
tunnel FET (TFET);
19.
A Noise Aware CML Latch Modelling for Large System Simulation
机译:
用于大型系统仿真的噪声感知CML闩锁建模
作者:
Bhatta D.
;
Bannerjee S.
;
Chatterjee A.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
Markov processes;
clocks;
flip-flops;
integrated circuit modelling;
integrated circuit noise;
mixed analogue-digital integrated circuits;
Markov chain based model;
analog blocks;
clock waveforms;
closed loop system dynamics;
continuous-time domain;
digital control blocks;
digital latches;
discrete-time domain;
high speed communication systems;
input waveforms;
latch transition probabilities;
noise aware CML latch modelling;
white noise;
Clocks;
Equations;
Integrated circuit modeling;
Latches;
Load modeling;
Mathematical model;
Noise;
latch modeling;
mixed signal simulation;
noise modeling;
20.
A Design Approach for Compressor Based Approximate Multipliers
机译:
基于压缩器的近似乘法器设计方法
作者:
Maheshwari N.
;
Zhixi Yang
;
Jie Han
;
Lombardi F.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
approximation theory;
digital arithmetic;
image processing;
multiplying circuits;
approximate computing;
arithmetic circuits;
compressor based approximate multiplier design;
delay reduction;
image processing application;
power reduction;
recursive multiplication;
Accuracy;
Adders;
Delays;
Image coding;
PSNR;
Approximate computing;
compressor;
multiplier;
21.
A Wide Dynamic-Range Low-Power Signal Conditioning Circuit for Low-Side Current Sensing Application
机译:
用于低侧电流检测应用的宽动态范围低功率信号调理电路
作者:
Rahul T.
;
Sahoo B.
;
Arya S.
;
Parvathy S.J.
;
Vulligaddala V.B.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
CMOS integrated circuits;
analogue-digital conversion;
delta-sigma modulation;
electric current measurement;
electric sensing devices;
flicker noise;
integrated circuit noise;
operational amplifiers;
programmable circuits;
sampling methods;
signal conditioning circuits;
switched capacitor networks;
AMS CMOS process;
analog-to-digital converter;
closed loop SC-PGA architecture;
current 2 mA;
double sampling technique;
flicker noise;
gain 80 dB;
level-shifting circuit;
low-side current sensing application;
multibit second order ΔΣ-ADC design;
offset noise;
op amp;
rail-to-rail input common mode;
settling requirement;
size 0.35 mum;
slew- rate requirement;
supply voltage variation;
switched capacitor programmable gain amplifier;
voltage 3.3 V;
wide dynamic-range low-power signal conditioning circuit;
Capacitors;
Clocks;
Electronics packaging;
Gain;
Noise;
Operational amplifiers;
Sensors;
Low-side current sensing;
PGA;
double sampling;
second-order #x0394;
#x03A3;
-ADC;
22.
ARGUS: A Framework for Rapid Design and Prototype of Heterogeneous Multicore Systems in FPGA
机译:
ARGUS:FPGA中异构多核系统快速设计和原型的框架
作者:
Ambrose J.A.
;
Tuo Li
;
Murphy D.
;
Gargg S.
;
Higgins N.
;
Parameswaran S.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
field programmable gate arrays;
logic design;
multiprocessing systems;
ARGUS;
FPGA;
automated prototyping;
heterogeneous multicore systems;
rapid design;
Emulation;
Field programmable gate arrays;
Hardware;
IP networks;
Middleware;
Multicore processing;
23.
Evaluating a Hardware-Based Approach for Detecting Resistive-Open Defects in SRAMs
机译:
评估基于硬件的方法来检测SRAM中的电阻性开路缺陷
作者:
Lavratti F.
;
Bolzani Poehls L.M.
;
Vargas F.
;
Calimera A.
;
Macii E.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
SRAM chips;
fault diagnosis;
logic testing;
system-on-chip;
NCL;
OCCS;
SRAM;
hardware-based approach;
neighbourhood comparison logic;
on-chip current sensors;
process variation;
resistive-open defect detection;
static random access memories;
Circuit faults;
Monitoring;
Resistance;
Resistors;
SRAM cells;
System-on-chip;
Neighborhood Comparison Logic;
On-Chip Current Sensor;
Resistive-Open Defects;
SRAM;
24.
Towards a Real-Time Campus-Scale Water Balance Monitoring System
机译:
建立实时的校园规模水平衡监测系统
作者:
Kudva V.D.
;
Nayak P.
;
Rawat A.
;
Anjana G.R.
;
Sheetal Kumar K.R.
;
Amrutur B.
;
Mohan Kumar M.S.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
cloud computing;
computerised monitoring;
level measurement;
microcontrollers;
microsensors;
network servers;
tanks (containers);
water resources;
battery operated sensor node;
campus water resource management;
cloud server;
hub system;
microcontroller;
real-time campus-scale water balance monitoring system;
spoke system;
subgigahertz radio;
tank;
ultrasound level sensor;
word length 16 bit;
Acoustics;
Logic gates;
Monitoring;
Real-time systems;
Reservoirs;
Water pollution;
Real time monitoring;
Ultrasonic Level Sensors;
Water Distribution Systems;
25.
Design of a Compact Reversible Carry Look-Ahead Adder Using Dynamic Programming
机译:
基于动态编程的紧凑型可逆携带式超前加法器设计
作者:
Lisa N.J.
;
Babu H.M.H.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
adders;
dynamic programming;
logic design;
RCLA;
RPA circuit;
carry generation signal;
carry propagation signal;
compact reversible carry look-ahead adder;
dynamic programming;
garbage output;
quantum cost;
reversible partial adder circuit;
Adders;
Algorithm design and analysis;
Complexity theory;
Delays;
Dynamic programming;
Hardware;
Logic gates;
Carry Look-Ahead Adder;
Garbage Output;
Logic Design;
Quantum Cost;
Reversible Computing;
26.
A Recursive Model for Smooth Approximation to Wirelength and Its Impact on Analytical Placement
机译:
平滑逼近线长的递归模型及其对分析位置的影响
作者:
Ray B.N.B.
;
Balachandran S.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
approximation theory;
integrated circuit design;
integrated circuit interconnections;
iterative methods;
recursive estimation;
ABS wire length model;
HPWL;
LSE wire length model;
WA wire length model;
analytical placement engines;
half-perimeter wire length;
iterative models;
log sum-exp wire length model;
recursive wire length model;
smooth approximation;
weighted average wire length model;
Analytical models;
Approximation methods;
Engines;
Integrated circuit modeling;
Optimization;
Runtime;
Upper bound;
27.
A Nonlinear Analytical Optimization Method for Standard Cell Placement of VLSI Circuits
机译:
VLSI电路标准单元放置的非线性分析优化方法
作者:
Pawanekar S.
;
Trivedi G.
;
Kapoor K.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
VLSI;
conjugate gradient methods;
integrated circuit design;
nonlinear programming;
Amoeba;
Capo;
IBM version 2 benchmarks;
Kapees2;
NTUPlace3;
VLSI circuits;
VLSI standard cell placement;
conjugate gradient method;
feng shui;
nonlinear analytical optimization method;
nonlinear equations;
nonlinear programming;
placement engine;
quadratic optimization;
reduced net list;
Benchmark testing;
Equations;
Linear programming;
Mathematical model;
Optimization;
Standards;
Very large scale integration;
Conjugate Gradient;
Nonlinear Optimization;
Standard Cell Placement;
VLSI Placement;
28.
A High-Performance Energy-Efficient Hybrid Redundant MAC for Error-Resilient Applications
机译:
用于错误恢复应用的高性能节能混合冗余MAC
作者:
Dutt S.
;
Chauhan A.
;
Bhadoriya R.
;
Nandi S.
;
Trivedi G.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
approximation theory;
digital arithmetic;
digital signal processing chips;
Approx MAC unit;
DSP;
SPAA metrics;
approximate computing;
approximate radix-2 hybrid redundant multiply-and-accumulate unit;
digital signal processing;
embedded JPEG-E-X IP core architecture;
error-resilient applications;
high-performance energy-efficient hybrid redundant MAC;
multiply-and-accumulate operation;
speed-power-accuracy-area metrics;
Adders;
Approximation algorithms;
Approximation methods;
Computer architecture;
Digital signal processing;
Measurement;
Silicon;
Approximate Computing;
Error Resilient Application;
Hybrid Redundant Number System;
Multiply-and-Accumulate Unit;
29.
Can You Trust Your Memory Trace? A Comparison of Memory Traces from Binary Instrumentation and Simulation
机译:
您可以信任您的内存跟踪吗?二进制仪器和仿真中的存储器轨迹比较
作者:
Nilakantan S.
;
Lerner S.
;
Hempstead M.
;
Taskin B.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
application program interfaces;
computerised instrumentation;
digital simulation;
multi-threading;
multiprocessing systems;
synchronisation;
API function call;
DBI;
dynamic binary instrumentation;
intrinsic nondeterminism;
memory trace;
multiple core system;
multithreaded application;
system simulation framework;
user space condition synchronization;
Benchmark testing;
Computational modeling;
Context;
Instruction sets;
Instruments;
Libraries;
Load modeling;
30.
Tutorial T9: Dealing with Startup Issues in Low Power Mixed Signal SoCs
机译:
教程T9:处理低功耗混合信号SoC中的启动问题
作者:
Ganesan S.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
low-power electronics;
mixed analogue-digital integrated circuits;
system-on-chip;
analog startup problem;
bandgap reference circuits;
current limiting;
current reference circuits;
failure mechanism;
linear regulators;
low power mixed signal SoC;
multiple power rail systems;
power on reset circuit;
power supply sequencing;
startup circuit design self-biased reference circuits;
startup issues;
system on a chip;
voltage reference circuits;
zero-power circuit;
Integrated circuit modeling;
Low-power electronics;
Power supplies;
Robustness;
System-on-chip;
Tutorials;
Very large scale integration;
31.
Embedded Tutorial ET1: Better-than-Worst-Case Timing Designs
机译:
嵌入式教程ET1:比最坏情况下的时序设计
作者:
Singh A.D.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
clocks;
error detection;
flip-flops;
integrated circuit design;
logic design;
timing circuits;
CMOS technology;
arithmetic circuits;
carry completion signaling;
circuit functional blocks;
circuit inactivity;
clock signal;
data flow systems;
error detection based recovery;
error detection circuits;
flip-flop duplication;
flip-flop inputs;
flip-flop meta-stability;
handshaking control protocol;
hold latches;
input based timing prediction;
path buffering;
path delays;
power efficiency;
ripple carry adders;
static power;
statistical variability;
switching signals;
synchronous systems;
timing designs;
timing error detection approach;
worst-case switching delay;
Clocks;
Delays;
Educational institutions;
Flip-flops;
Synchronization;
Very large scale integration;
32.
Tutorial T3: Error Resilient Real-Time Embedded Systems: Computing, Communications and Control
机译:
教程T3:防错实时嵌入式系统:计算,通信和控制
作者:
Abraham J.A.
;
Chatterjee A.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
control engineering computing;
embedded systems;
linear systems;
nonlinear control systems;
robots;
signal processing;
RF circuits;
RF processing;
analog signal;
communications;
computing;
digital signal processing;
error resilient real-time embedded systems;
linear control;
mixed-signal processing;
nonlinear control;
online testing methods;
robotic system;
transient errors;
video sensor;
Awards activities;
Embedded systems;
Radio frequency;
Real-time systems;
Robot sensing systems;
Very large scale integration;
33.
Tutorial T4: MEMS: Design, Fabrication, and their Applications as Chemical and Biosensors
机译:
教程T4:MEMS:设计,制造及其在化学和生物传感器中的应用
作者:
Kale N.S.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
DNA;
MOSFET;
accelerometers;
bioMEMS;
biomimetics;
biosensors;
cantilevers;
chemical sensors;
elemental semiconductors;
logic circuits;
microactuators;
microfluidics;
micromirrors;
nanosensors;
pressure sensors;
radio transceivers;
silicon;
3-dimensional mechanical structures;
Coventorware;
DNA chips;
Intellisuite;
MOSFET;
NEMS;
SU-8 polymeric materials;
Si;
accelerometer;
actuators;
automobile electronics;
bioMEMS;
biochemical assay;
biological material;
biomedical assay;
biomimetic material;
biosensors;
chemical sensors;
consumer electronics;
dc power consumption;
digital micromirror devices;
logic circuits;
microTAS;
microcantilever;
microelectronic devices;
microfluidics;
microheaters;
micromachined electromechanical systems;
microsensors;
pressure sensor;
silicon based mechanical drivers;
smart cell phones;
transceiver fabrication;
wireless enabled devices;
Chemicals;
Micromechanical devices;
Nanobioscience;
Silicon;
Tutorials;
Very large scale integration;
34.
Tutorial T5: High Performance Low Power Designs - Challenges and Best practices in Design, Verification and Test
机译:
教程T5:高性能低功耗设计-设计,验证和测试中的挑战和最佳实践
作者:
Tamarapalli N.
;
Vallur P.
;
Kulkarni S.S.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
integrated circuit design;
integrated circuit yield;
logic design;
silicon;
system-on-chip;
SOC-level;
high performance IC;
low power designs;
mixed-signal IP;
process variability issues;
semiconductor yield;
silicon behavior predictability;
size 65 nm;
system-level verification;
Best practices;
System-on-chip;
Testing;
Tutorials;
Very large scale integration;
35.
Tutorial T1: Neuromorphic Computing - Algorithms, Devices and Systems
机译:
教程T1:神经形态计算-算法,设备和系统
作者:
Rajendran B.
;
Ganguly U.
;
Suri M.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
brain;
neural chips;
algorithmic idea;
computational system;
core functional feature;
human brain;
neuromorphic computing;
power-efficient nanoscale material;
system level deployment;
Materials;
Neuromorphics;
Nonvolatile memory;
Patents;
Tutorials;
36.
Tutorial T6: FinFET Device Circuit Co-design: Issues and Challenges
机译:
教程T6:FinFET器件电路协同设计:问题与挑战
作者:
Dasgupta S.
;
Anand B.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
MOSFET;
SRAM chips;
foundries;
logic circuits;
permittivity;
semiconductor industry;
semiconductor technology;
FinFET device circuit codesign;
Intel announcement;
SRAM applications;
TSMC announcement;
circuit immunity;
dual spacer;
logic circuit;
permittivity spacers;
physical architectures;
physical configurations;
random variations;
semiconductor foundry;
semiconductor industry;
semiconductor technology;
size 14 nm;
size 16 nm;
tri-gate technology;
FinFETs;
Performance evaluation;
Random access memory;
Tutorials;
Very large scale integration;
37.
On-the-Fly Donut Formation in Compiled Memory
机译:
编译内存中的动态甜甜圈形成
作者:
Singh D.
;
Garg I.
;
Sachan V.
;
Nalawar P.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
RC circuits;
SRAM chips;
compiler generators;
disc storage;
timing circuits;
transistors;
RC extraction;
SRAM memory;
disk space;
donut generation;
instance extraction;
memory compiler characterization;
memory size 80 KByte;
nontiming critical bitcell array;
normal simulation machines;
on-the-fly donut creation formation flow;
timing data collection;
timing simulation accuracy;
timing-critical bitcells;
transistors;
Accuracy;
Arrays;
Delays;
Flowcharts;
Niobium;
Silicon;
Characterization;
Donut Generation;
Extraction;
Memory Compiler;
38.
All Optical Implementation of Mach-Zehnder Interferometer Based Reversible Sequential Counters
机译:
基于马赫曾德尔干涉仪的可逆顺序计数器的全光学实现
作者:
Dutta P.
;
Bandyopadhyay C.
;
Rahaman H.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
Mach-Zehnder interferometers;
counters;
optical design techniques;
optical switches;
semiconductor optical amplifiers;
sequential circuits;
MZI switches;
Mach-Zehnder interferometer;
SOA;
all optical reversible implementation;
design complexity;
memory elements;
reversible sequential counters;
semiconductor optical amplifier;
Logic gates;
Optical design;
Optical interferometry;
Optical switches;
Radiation detectors;
Semiconductor optical amplifiers;
Mach-Zehnder Interferometer (MZI);
Reversible computing;
counter;
garbage;
optical cost;
optical delay;
39.
Implementation of NOR Logic Based on Material Implication on CMOL FPGA Architecture
机译:
基于实质性含义的NOR逻辑在CMOL FPGA架构上的实现
作者:
Mane P.
;
Talati N.
;
Riswadkar A.
;
Jasani B.
;
Ramesha C.K.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
CMOS logic circuits;
field programmable gate arrays;
logic gates;
CMOL FPGA architecture;
CMOS layer;
NOR block;
NOR logic;
configurable logic blocks;
material implication;
memristor based nanocrossbar layer;
nanocrossbar memory;
CMOS integrated circuits;
Computer architecture;
Field programmable gate arrays;
Logic gates;
Memristors;
Resistance;
Wires;
40.
An FPGA-Based Architecture for Local Similarity Measure for Image/Video Processing Applications
机译:
基于FPGA的图像/视频处理应用局部相似性度量架构
作者:
Pandey J.G.
;
Karmakar A.
;
Shekhar C.
;
Gurunarayanan S.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
DRAM chips;
field programmable gate arrays;
image processing;
probability;
video signal processing;
Bhattacharyya coefficient;
Block RAM;
DDR2 SDRAM;
DSP48E slices;
FPGA-based architecture;
Virtex-5 xc5vfx70t FPGA device;
Xilinx ML-507 platform;
antilogarithmic computing units;
diverse signal-processing;
image-video processing;
local image statistics;
local similarity measure;
logarithmic number system;
probability density functions;
single-cycle read-modify-write operations;
Computer architecture;
Field programmable gate arrays;
Hardware;
Histograms;
Image color analysis;
Kernel;
Random access memory;
Bhattacharyya coefficient;
FPGA Platform;
Local similarity measure;
VLSI architecture for image and video processing;
fixed-point architecture;
41.
Recessed MOSFET in 28 nm FDSOI for Better Breakdown Characteristics
机译:
采用28 nm FDSOI的嵌入式MOSFET,具有更好的击穿特性
作者:
Kranthi N.K.
;
Sithanandam R.
;
Komaragiri R.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
MOSFET;
semiconductor device breakdown;
silicon-on-insulator;
DC characteristics;
FDSOI;
breakdown characteristics;
breakdown voltage;
drain-channel junction;
electric field distributions;
fully depleted silicon on insulator;
ground plane;
recessed MOSFET;
size 28 nm;
Electric breakdown;
Electric fields;
Junctions;
Logic gates;
MOSFET;
Resistance;
Transconductance;
Breakdown voltage;
FDSOI;
Ground Plane;
Recessed;
42.
Exploring Scope of Power Reduction with Constrained Physical Synthesis
机译:
受限物理综合探索降功率的范围
作者:
Guha K.
;
Saha S.
;
Nigaglioni R.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
electronic design automation;
integrated circuit design;
logic design;
optimisation;
constrained library access approach;
constrained physical synthesis;
constraint based library access;
power optimization engine;
power optimization perspective;
power reduction;
regular library access approach;
relative power criticality;
threshold voltage variants;
Engines;
Libraries;
Logic gates;
Mathematical model;
Optimization;
Timing;
EDA;
low power;
physical synthesis;
43.
Design of 3D Antennas for 24 GHz ISM Band Applications
机译:
用于24 GHz ISM频段应用的3D天线设计
作者:
Sravani P.
;
Rao M.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
antenna feeds;
microstrip antennas;
microwave antennas;
planar antennas;
3D antenna configurations;
3D antenna design;
3D conducting channels;
3D electromagnetic tool;
3D structures;
Ansoft HFSS;
ISM band;
antenna impedance;
antenna parameters;
chip functionalities;
frequency 24 GHz;
optimal 2D space;
planar patch antenna;
quarter wave transmission line;
surface current distribution;
three dimensional antenna;
Antenna measurements;
Patch antennas;
Solid modeling;
Surface impedance;
Three-dimensional displays;
Transmission line antennas;
24 GHz;
3D antennas;
ISM band;
high frequency antennas;
44.
Any Capacitor Stable LVR Using Sub-unity Gain Positive Feedback Loop in 65nm CMOS
机译:
在65nm CMOS中使用亚单位增益正反馈环路的任何电容器稳定LVR
作者:
Singh S.K.
;
Bansal N.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
CMOS integrated circuits;
capacitors;
circuit feedback;
circuit stability;
voltage regulators;
CMOS;
NMOS pass element;
capacitance 1 nF to 40 muF;
capacitor stable LVR;
current 0 mA to 115 mA;
linear voltage regulator;
load current step;
output capacitance value;
positive feedback loop;
size 65 nm;
sub-unity gain;
time 0.14 mus;
time 0.5 mus;
voltage 1.25 V;
voltage 1.6 V;
voltage 158 mV;
voltage 3 V;
CMOS integrated circuits;
Capacitance;
Capacitors;
Regulators;
System-on-chip;
Transient analysis;
Voltage control;
NMOS pass element;
capacitor-less;
linear voltage regulator;
positive feedback loop;
45.
Accurate Constant Transconductance Generation without Off-Chip Components
机译:
无需片上组件即可产生精确的恒定跨导
作者:
Mondal I.
;
Krishnapura N.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
CMOS integrated circuits;
MOSFET;
feedback;
CMOS technology;
MOSFET;
constant current reference;
constant voltage reference;
negative feedback control;
off-chip component;
process voltage and temperature invariant;
size 0.13 mum;
temperature 120 degC;
transconductance generation technique;
MOSFET;
Negative feedback;
Resistance;
Resistors;
System-on-chip;
Transconductance;
Mismatch;
Off-chip;
Transconductance;
46.
Rectilinear Steiner Clock Tree Routing Technique with Buffer Insertion in Presence of Obstacles
机译:
存在障碍物的带缓冲插入的直线型斯坦纳时钟树路由技术
作者:
Saha P.P.
;
Saha S.
;
Samanta T.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
VLSI;
buffer circuits;
clocks;
estimation theory;
integrated circuit design;
integrated circuit testing;
network routing;
BBLUE;
IBM;
ISPD 2010 benchmark;
Intel;
Steiner point insertion;
VLSI circuit design;
blockage look up and buffer estimation;
buffer insertion;
physical design constraint;
rectilinear steiner clock tree routing design technique;
skew minimization;
Benchmark testing;
Clocks;
Delays;
Minimization;
Routing;
Synchronization;
Wires;
Buffer Insertion;
Clock Tree;
Obstacle Avoiding Rectilinear Steiner Tree;
Skew Minimization;
VLSI Routing;
47.
Two Phase Write Scheme to Improve Low Voltage Write-ability in Medium-Density SRAMs
机译:
两相写入方案可提高中密度SRAM中的低压写入能力
作者:
Siddiqui M.S.M.
;
Sharad S.
;
Sharma Y.
;
Khanuja A.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
MOSFET;
SRAM chips;
electric breakdown;
hot carriers;
integrated circuit design;
integrated circuit reliability;
logic design;
low-power electronics;
SRAM architecture;
SRAM bit cell;
SRAM designs;
TDDB;
TSMC FinFET technology;
VDDMIN environment;
bit cell write margin;
gate oxide tox reliability;
hot carrier injection;
overdrive word line write assist circuits;
power supply rail;
size 16 nm;
time-dependent dielectric breakdown;
voltage 0.52 V;
voltage 85 mV;
word line voltage level;
write ability;
write scheme;
Circuit stability;
Computer architecture;
Delays;
Logic gates;
Microprocessors;
Multiplexing;
Random access memory;
Psuedo read;
Register files;
SNM improvement;
SRAM;
VDDMIN improvement;
Write cycle;
Write margin improvement;
48.
On the Analysis of Reversible Booth's Multiplier
机译:
可逆展位乘数分析
作者:
Sultana J.
;
Mitra S.K.
;
Chowdhury A.R.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
logic design;
multiplying circuits;
efficient design method;
reversible Booth multiplier;
reversible circuit design;
reversible circuits;
reversible gate;
reversible logic;
reversible paradigm;
Arrays;
Delays;
Equations;
Logic gates;
Microprocessors;
Vectors;
Booth's Multiplier;
Garbage Output;
Low power Design;
Quantum Cost;
49.
Smart Port Allocation for Adaptive NoC Routers
机译:
自适应NoC路由器的智能端口分配
作者:
James R.
;
Jose J.
;
Antony J.K.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
multiprocessing systems;
network routing;
network-on-chip;
SoC;
adaptive NoC routers;
buffered deflection routers;
channel wastage;
multiple processing cores;
network on chip;
packet latency;
pipeline register;
pipeline stage delay;
router microarchitecture;
smart port allocation;
system on chip;
unwanted intra-router movement;
Buffer storage;
Pipelines;
Ports (Computers);
Registers;
Resource management;
Routing;
Switches;
buffer-pool;
deflection routing;
router pipeline;
50.
On Event Driven Modeling of Continuous Time Systems
机译:
连续时间系统的事件驱动建模
作者:
Juneja D.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
circuit feedback;
continuous time filters;
discrete event simulation;
continuous time filters;
event driven modeling;
feedback circuits;
numerical instability;
speed enhancement;
Delays;
Frequency conversion;
Gain;
Integrated circuit modeling;
Mathematical model;
Numerical models;
Phase locked loops;
Behavioral Modeling;
Event Driven Simulation;
Real Number Modeling;
51.
Energy Aware Computation Driven Approximate DCT Architecture for Image Processing
机译:
能量感知计算驱动的近似DCT架构进行图像处理
作者:
Kaushal V.
;
Garg B.
;
Jaiswal A.
;
Sharma G.K.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
approximation theory;
discrete cosine transforms;
field programmable gate arrays;
image processing;
CMOS technology;
Virtex - 6 FPGA;
approximate DCT architecture;
core compute-intensive component;
discrete cosine transform;
energy aware computation;
energy crisis;
image processing;
image quality assessment parameters;
inter pixel approximation;
multimedia devices;
multiplicand value decision;
pixels transitive behavior;
Adders;
Approximation methods;
Computer architecture;
Discrete cosine transforms;
Equations;
Measurement;
Standards;
Discrete Cosine Transform;
FPGA;
Image quality assessment;
Inter pixel approximation;
JPEG;
Transitive behavior;
52.
Efficient Peak Power Estimation Using Probabilistic Cost-Benefit Analysis
机译:
使用概率成本效益分析的有效峰值功率估计
作者:
Hajimiri H.
;
Rahmani K.
;
Mishra P.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
circuit reliability;
combinational circuits;
cost-benefit analysis;
logic design;
logic gates;
power consumption;
probability;
sequential circuits;
combinational benchmark circuit;
digital circuits;
dynamic power dissipation;
gate transition blocking;
high fan-out gates;
optimistic design;
peak power consumption estimation;
power attacks;
power virus generation technique;
probabilistic cost-benefit analysis;
sequential benchmark circuit;
switching activity;
zero-delay model;
Estimation;
Integrated circuit modeling;
Logic gates;
Power demand;
Switches;
Switching circuits;
Vectors;
53.
Block-Level Electro-Migration Analysis (BEMA) for Safer Product Life
机译:
块级电迁移分析(BEMA)可延长产品寿命
作者:
Gupta R.
;
Bhargava A.
;
Panemangalore R.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
electromigration;
integrated circuit interconnections;
integrated circuit metallisation;
integrated circuit reliability;
Custom IP;
block-level electromigration analysis;
interconnects;
metallization;
product cycle time;
Correlation;
Electromigration;
Layout;
Metals;
Reliability;
Runtime;
Stress;
54.
An Efficient Transition Detector Exploiting Charge Sharing
机译:
利用电荷共享的高效过渡检测器
作者:
Yu Wang
;
Singh A.D.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
discharges (electric);
flip-flops;
microprocessor chips;
short-circuit currents;
BTWC timing design;
TDCS design;
better-than-worst-case timing design;
flip-flops;
metastability detection;
microprocessors;
online error;
short circuit based discharge;
timing errors;
transition detector charge sharing;
Clocks;
Delays;
Detectors;
Discharges (electric);
Latches;
Threshold voltage;
Transistors;
Better-Than-Worst-Case deisgn;
PVT variations;
charge sharing;
error detection;
short circuit;
transition detector;
55.
Optimal Test Scheduling of Stacked Circuits under Various Hardware and Power Constraints
机译:
各种硬件和功率约束下的堆叠电路最佳测试计划
作者:
Millican S.K.
;
Saluja K.K.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
integrated circuit design;
integrated circuit testing;
scheduling;
system-on-chip;
DVFS hardware;
IC;
SoC test scheduling;
dynamic voltage and frequency scaling hardware;
hardware constraint;
power constraint;
scheduling complexity;
silicon device testing;
stacked integrated circuit;
system-on-chip test scheduling;
test cost reduction;
Benchmark testing;
Hardware;
Pins;
Schedules;
Scheduling;
System-on-chip;
DVFS;
SoC Test;
power constraints;
56.
Thermal-Aware Test Data Compression Using Dictionary Based Coding
机译:
基于字典的编码的热感知测试数据压缩
作者:
Karmakar R.
;
Chattopadhyay S.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
electronic engineering computing;
integrated circuit testing;
vectors;
chip temperature;
dictionary based coding;
temperature reduction;
test data volume;
test vector;
thermal-aware test data compression;
transition count;
Benchmark testing;
Circuit faults;
Dictionaries;
Power demand;
Temperature distribution;
Test data compression;
Compression;
dictionary based coding;
don't-care bits;
temperature reduction;
57.
Bandwidth Adaptive Nanophotonic Crossbars with Clockwise/Counter-clockwise Optical Routing
机译:
具有顺时针/逆时针光学路由的带宽自适应纳米光子交叉开关
作者:
Kennedy M.
;
Kodi A.K.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
bandwidth allocation;
computer architecture;
multiprocessing systems;
nanophotonics;
bandwidth adaptive nanophotonic crossbar;
crossbar topology;
many-core processor;
nanophotonic crossbar interconnect architecture;
optical routing;
Bandwidth;
Optical fiber networks;
Optical losses;
Optical receivers;
Optical ring resonators;
Optical waveguides;
Waveguide lasers;
58.
Design of High Speed Ternary Full Adder and Three-Input XOR Circuits Using CNTFETs
机译:
利用CNTFET设计高速三元全加法器和三输入XOR电路
作者:
Murotiya S.L.
;
Gupta A.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
adders;
carbon nanotube field effect transistors;
logic design;
logic gates;
voltage dividers;
CNTFET technology;
PDP;
Stanford CNTFET model;
carbon nano tube field effect transistor technology;
decoding unit;
energy efficient three-input ternary XOR circuit;
high speed TFA cell;
high speed ternary full adder cell;
power-delay product;
pull-down networks;
resistive voltage divider;
size 32 nm;
sum generation unit;
symmetric pull-up networks;
temperature variations;
voltage variations;
Adders;
CNTFETs;
Delays;
Generators;
Logic gates;
Simulation;
Carbon nano tube (CNT) field effect transistor (CNTFET);
Power-delay product (PDP);
Ternary XOR;
Ternary full adder (TFA);
Ternary logic;
59.
Exploration of Migration and Replacement Policies for Dynamic NUCA over Tiled CMPs
机译:
平铺CMP上的动态NUCA迁移和替换策略的探索
作者:
Das S.
;
Kapoor H.K.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
cache storage;
memory architecture;
microprocessor chips;
multiprocessing systems;
CPI;
DNUCA architectures;
SNUCA;
TCMP;
cache designs;
centralized cache banks;
chip multiprocessor;
concurrent applications;
cycles per instruction;
dynamic NUCA;
fixed address mapping policy;
large data-centers;
migration policies;
miss-rate;
multicore processors;
next generation scalable architecture;
replacement policies;
small scale embedded systems;
static NUCA;
tiled CMP;
Benchmark testing;
Computer architecture;
Power system faults;
Power system protection;
Program processors;
System-on-chip;
Very large scale integration;
Block migration;
CMP;
Dynamic NUCA;
Last Level Cache;
NUCA;
Tiled-CMP;
60.
Analysis of Second-Order Effect Components of Drain Conductance and Its Implication on Output Resistance of Wilson Current Mirror
机译:
漏极电导的二阶效应分量分析及其对威尔逊电流镜输出电阻的影响
作者:
Singh K.
;
Bhattacharyya A.B.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
analogue circuits;
current mirrors;
electric admittance;
interpolation;
modulation;
sensitivity analysis;
BSIM3v3 model PTM;
CLM;
DIBL;
EKV model;
Early voltage;
IC;
VFMR;
Wilson current mirror resistance;
analog circuit;
channel length modulation;
drain conductance;
drain induced barrier lowering;
fixed drain voltage;
interpolation equation;
intrinsic voltage gain;
inversion coefficient;
inversion level function;
overdrive voltage;
predictive technology model;
resistance sensitivity;
second-order effect component analysis;
shape factor;
single stage common source transistor;
size 180 nm;
small-signal model analysis;
transresistance expression;
velocity saturation;
vertical field mobility reduction;
Equations;
Integrated circuit modeling;
Logic gates;
Mathematical model;
Mirrors;
Resistance;
DIBL;
VFMR;
channel length modulation;
drain conductance subcomponents;
intrinsic voltage gain;
inversion coefficient;
output resistance;
sensitivity analysis;
velocity saturation;
61.
On-the-Fly Mapping for Synthesizing Dynamic Domino Circuits
机译:
动态合成动态多米诺电路的动态映射
作者:
Kadiyala S.P.
;
Samanta D.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
logic circuits;
logic design;
DAAM;
delay area aware mapping;
domino logic circuit;
equivalence table;
library free mapping;
node mapping algorithm;
on-the-fly mapping technique;
Benchmark testing;
Delays;
Libraries;
Logic gates;
Optimization;
Sociology;
Transistors;
Domino logic;
cell re-ordering;
logic effort;
on-the-fly mapping;
62.
Hardware Solution for Real-Time Face Recognition
机译:
实时人脸识别的硬件解决方案
作者:
Mahale G.
;
Mahale H.
;
Goel A.
;
Nandy S.K.
;
Bhattacharya S.
;
Narayan R.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
computational complexity;
face recognition;
principal component analysis;
radial basis function networks;
RBFNN;
Virtex-6 LX550T FPGA;
WMPCA;
computational complexity;
functional correctness testing;
independent modular computations;
off-chip memory;
on-chip resources;
parallel streams;
radial basis function neural network;
real-time face recognition;
real-time response;
scalable modular hardware solution;
weighted modular principle component analysis;
Accuracy;
Computer architecture;
Databases;
Face recognition;
Hardware;
Real-time systems;
Vectors;
Architecture;
FPGA;
Face Recognition;
RBFNN;
Real-time;
WMPCA;
63.
Accelerating SVM on Ultra Low Power ASIP for High Throughput Streaming Applications
机译:
在超低功耗ASIP上加速SVM,以实现高吞吐量流应用
作者:
Gupta A.
;
Pal A.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
graphics processing units;
image processing;
image recognition;
instruction sets;
low-power electronics;
support vector machines;
video signal processing;
video streaming;
ADL-based tool;
ARM Cortex-A8;
GPU;
SVM;
application specific instruction processor;
architectural description language-based tool;
base RISC processor;
battery power consumption;
classification tasks;
embedded systems;
embedded vision;
embedded vision-domain;
high-throughput streaming application;
image recognition;
pattern recognition;
pedestrian detection algorithm;
power 6.5 mW;
processor performance;
support vector machines;
ultralow-power ASIP;
video recognition;
Algorithm design and analysis;
Random access memory;
Registers;
Support vector machine classification;
Throughput;
Vectors;
ASIP;
SVM;
64.
Analysis and Optimization of Programmable Delay Elements for 2-Phase Bundled-Data Circuits
机译:
两相捆绑数据电路可编程延迟元件的分析和优化
作者:
Heck Guilherme
;
Heck Leandro S.
;
Singhvi Ajay
;
Moreira Matheus T.
;
Beerel Peter /A/.
;
Calazans Ney L. V.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
CMOS logic circuits;
asynchronous circuits;
circuit optimisation;
delay circuits;
power consumption;
2-phase bundled-data asynchronous circuits;
bulk CMOS technology;
circuit design;
delay margins;
power consumption;
programmable delay elements;
size 65 nm;
transistor sizing strategy;
voltage scaling;
Delay lines;
Delays;
Inverters;
Logic gates;
MOS devices;
Propagation delay;
Transistors;
2-phase bundled-data;
Asynchronous circuits;
Delay elements;
Voltage scaling;
65.
Noninvasive Cuffless Blood Pressure Measurement by Vascular Transit Time
机译:
通过血管传输时间进行无创无袖带血压测量
作者:
Shukla S.N.
;
Kakwani K.
;
Patra A.
;
Lahkar B.K.
;
Gupta V.K.
;
Jayakrishna A.
;
Vashisht P.
;
Sreekanth I.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
Android (operating system);
Bluetooth;
biomedical telemetry;
blood;
blood pressure measurement;
diseases;
health care;
injuries;
medical signal processing;
paediatrics;
phonocardiography;
photoplethysmography;
Bluetooth module;
captured signals;
commercial cuff-based digital blood pressure measuring device;
cuff-based noninvasive methods;
end-to-end prototype;
heart activity signal capturing;
infants;
infection;
injured people;
invasive methods;
low-cost fully realized implementation;
noninvasive cuffless blood pressure measurement;
obese people;
offline processing;
personal health care;
phonocardiogram;
photoplethysmograph;
physiological parameters;
user interactive android application;
vascular transit time;
Accuracy;
Biomedical monitoring;
Blood pressure;
Digital filters;
Heart;
Phonocardiography;
Pressure measurement;
Blood Pressure;
Cuffless;
PCG;
PPG;
Vascular Transit Time (VTT);
66.
DFT Technique for Quick Characterization of Flash Offset in Pipeline ADCs
机译:
DFT技术可快速表征流水线ADC中的闪存偏移
作者:
Nair P.
;
Viswanathan N.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
analogue-digital conversion;
discrete Fourier transforms;
DFT technique;
analog to digital converter;
coarse flash;
discrete Fourier transforms;
flash offset;
measurement setup;
nonSHA architecture;
pipeline ADC;
quick characterization;
sample and hold amplifier;
standard single-tone test;
Discrete Fourier transforms;
Frequency measurement;
Heuristic algorithms;
Measurement uncertainty;
Pipelines;
Redundancy;
Standards;
Differential Non-Linearity (DNL);
Multiplying Digital to Analog Converter (MDAC);
Process;
Sample and Hold Amplifier (SHA);
Voltage and Temperature (PVT);
67.
Scaling the UVM_REG Model towards Automation and Simplicity of Use
机译:
将UVM_REG模型扩展为自动化和使用简便
作者:
Jain A.
;
Gupta R.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
application program interfaces;
formal verification;
program testing;
software libraries;
API;
ATE test vectors development;
IP level verification;
IP-XACT based tools;
Internet of Things;
IoT;
OS based capability;
SV UVM language;
SoC level register;
SoC level verification;
UVM register package;
UVM_REG register model;
automation;
built-in test sequences library;
customized code;
memory accesses;
memory burst operation;
memory sequence;
memory testing;
processor programmable registers;
register sequence;
register test;
test development;
verification environment code;
verification environments;
IP networks;
Memory management;
Registers;
Standards;
System-on-chip;
Testing;
Writing;
IP-XACT;
Register Model;
Register Sequences;
System Verilog;
UVM REG;
Universal Verification Methodology (UVM);
68.
Integrated 16-Channel Transmit and Receive Beamforming ASIC for Ultrasound Imaging
机译:
用于超声成像的集成式16通道发送和接收波束形成ASIC
作者:
Dusa C.
;
Kalalii S.
;
Rajalakshmi P.
;
Rao O.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
application specific integrated circuits;
array signal processing;
biomedical transducers;
biomedical ultrasonics;
coaxial cables;
image reconstruction;
integrated circuit design;
medical image processing;
probes;
synchronisation;
ultrasonic imaging;
Design Compiler;
Rx beam former;
Rx beamforming ASIC;
Synopsys ICC;
Tx beam former;
Tx beamforming ASIC;
UMC technology;
analog front end electronics;
application specific integrated circuit;
coaxial cables;
delay profile;
digitized echoes;
frequency 40 MHz;
image reconstruction;
medical frequencies;
multielement transducer array;
power 38 mW;
power dissipation;
programmable transmit beam former;
pulse pattern;
pulse-echo mode;
receive beam former;
receive beamforming ASIC;
scan lines;
size 130 nm;
size 5.29 mm;
time 1.25 ns;
time 163.85 mus;
time 3.125 ns;
transducer elements;
transmit beamforming ASIC;
transmit channel;
transmit frequency;
transmit pulse length;
ultrasound imaging;
ultrasound probe head;
ultrasound systems;
user control;
Embedded systems;
Very large scale integration;
ASIC implementation;
Design compiler;
Integrated circuit compiler;
Receive beamforming;
Transmit beamforming;
69.
Reliability Enhancement of SoCs Based on Dynamic Memory Access Profiling in Conjunction with PVT Monitoring
机译:
基于动态内存访问分析与PVT监控相结合的SoC可靠性增强
作者:
Baranwal D.
;
Singh D.
;
Soyeb K.
;
Rout S.S.
;
Deb S.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
integrated circuit reliability;
semiconductor storage;
system-on-chip;
PVT monitoring;
RAIMM;
SoC;
architectural framework;
direct memory access engine;
dynamic memory access profiling;
memory failure;
memory reliability status;
multiprocessor System-On-Chip;
on-chip memories;
reliability aware intelligent memory management;
reliability enhancement;
Memory management;
Monitoring;
Program processors;
Reliability;
System-on-chip;
Temperature measurement;
Temperature sensors;
Memory Reliability;
System prototyping with virtual platform;
dynamic memory remapping;
intra-die variation;
memory characterization;
memory ranking;
70.
DyMeP: An Infrastructure to Support Dynamic Memory Binding for Runtime Mapping in CGRAs
机译:
DyMeP:支持动态内存绑定以在CGRA中运行时映射的基础结构
作者:
Tajammul M.A.
;
Jafri S.M.A.
;
Ellerve P.
;
Hemani A.
;
Tenhunen H.
;
Plosila J.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
distributed shared memory systems;
reconfigurable architectures;
storage management;
CGRAs;
DyMeP;
coarse grained reconfigurable architectures;
compiler programmed memories;
computation layer;
distributed shared scratchpad memories;
dynamic application remapping;
dynamic memory binding;
fat binaries;
memory layer;
runtime mapping;
Delays;
Dynamic scheduling;
Hardware;
Memory management;
Routing;
Runtime;
Synchronization;
CGRA;
Coarse Grained Reconfigurable Architecture;
Dynamic Memory Binding;
NOC;
Network on Chip;
circuit switched network on chip;
late binding;
relative addressing;
71.
Robot Navigation Using Neuro-electronic Hybrid Systems
机译:
使用神经电子混合系统的机器人导航
作者:
George J.B.
;
Abraham G.M.
;
Amrutur B.
;
Sikdar S.K.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
collision avoidance;
neurocontrollers;
robots;
VLSI system;
biological neuronal system;
neuro-electronic hybrid system;
neuronal culture;
obstacle avoidance;
parallel processing;
robot navigation;
Decoding;
Electrodes;
Hardware;
Neurons;
Robot sensing systems;
Timing;
Cultured neural networks;
LSM;
Temporal Coding;
neuro-electronic hybrid systems;
72.
Way Halted Prediction Cache: An Energy Efficient Cache Architecture for Embedded Processors
机译:
暂停预测缓存的方式:节能高效的嵌入式处理器缓存体系结构
作者:
Mallya N.B.
;
Patil G.
;
Raveendran B.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
cache storage;
circuit simulation;
content-addressable storage;
embedded systems;
energy consumption;
microprocessor chips;
CACTI 5.3 simulator;
CASIM simulator;
SPEC benchmark program;
dynamic energy consumption;
embedded processor;
energy efficient cache architecture;
halt tag array;
halting cache architecture;
prediction circuit;
set associative cache;
way halted prediction cache;
Accuracy;
Arrays;
Benchmark testing;
Decoding;
Energy consumption;
Energy efficiency;
Program processors;
cache architecture;
energy efficient cache design;
way halting;
way predicting;
73.
Diagnostic Tests for Pre-bond TSV Defects
机译:
预键合TSV缺陷的诊断测试
作者:
Bei Zhang
;
Agrawal V.D.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
integer programming;
integrated circuit bonding;
integrated circuit testing;
linear programming;
three-dimensional integrated circuits;
3D stacked devices;
ILP model;
TSV network;
defect identification;
diagnostic tests;
integer linear programming model;
pre-bond TSV probing technique;
prebond TSV defects;
prebond TSV test time;
prebond testing;
through silicon via;
Circuit faults;
Electrical resistance measurement;
Needles;
Probes;
Resistance;
Testing;
Through-silicon vias;
3D stacked integrated circuits;
pre-bond TSV testing;
through silicon via (TSV) defects;
74.
FPGA Based Scalable Fixed Point QRD Core Using Dynamic Partial Reconfiguration
机译:
使用动态部分重配置的基于FPGA的可扩展定点QRD内核
作者:
Prabhu G.R.
;
Johnson B.
;
Rani J.S.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
Newton-Raphson method;
field programmable gate arrays;
matrix algebra;
phase shift keying;
systolic arrays;
BPSK symbol transmission;
DPR capability;
LUT based Newton-Raphson method;
QRD-RLS algorithm;
Xilinx Virtex-6 FPGA;
area utilization reduction;
dynamic partial reconfiguration capability;
dynamic power reduction;
givens rotation algorithm;
high performance adaptive equalizer;
inverse square root;
matrices;
mobile receiver;
pipelined 2D MAC;
scalable fixed point QRD architecture;
scalable fixed point QRD core;
systolic array architecture;
training mode;
unfolded 2D MAC;
Arrays;
Field programmable gate arrays;
Hardware;
Matrix decomposition;
Microprocessors;
Table lookup;
Givens rotation;
LUT Newton Raphson;
Partial reconfiguration;
QR decomposition;
Systolic array;
75.
Geometric Programming Formulation for Gate Sizing with Pipelining Constraints
机译:
带有流水线约束的浇口尺寸的几何编程公式
作者:
Naidu S.R.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
combinational circuits;
computational complexity;
convex programming;
flip-flops;
geometric programming;
sizing (materials processing);
NP-hard problems;
acyclic pipelining constraint optimization;
combinational circuit performance;
combined retiming-gate sizing problem;
convex optimization tool framework;
delay model;
geometric programming formulation;
glean valuable information;
physically moving registers;
Capacitance;
Delays;
Linear programming;
Logic gates;
Pipeline processing;
Registers;
Resistance;
NP-hard;
convex optimization;
gate sizing;
retiming;
76.
Comparison of Off-Chip Training Methods for Neuromemristive Systems
机译:
神经忆阻系统芯片外训练方法的比较
作者:
Merkel C.
;
Kudithipudi D.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
CMOS integrated circuits;
learning (artificial intelligence);
memristor circuits;
neural chips;
CMOS process variations;
feature training;
feature training method;
handwritten digit classification;
memristor process variations;
neuromemristive circuits;
neuromemristive systems;
nonlinear functions;
off-chip training methods;
pattern classification;
synapses;
training circuits;
weight programming method;
Accuracy;
CMOS integrated circuits;
Integrated circuit modeling;
Memristors;
Neurons;
Programming;
Training;
memristor;
neural networks;
neuromemristive systems;
neuromorphic;
77.
OcNoC: Efficient One-Cycle Router Implementation for 3D Mesh Network-on-Chip
机译:
OcNoC:3D Mesh片上网络的高效单周期路由器实现
作者:
Fernandes R.
;
Brahm L.
;
Webber T.
;
Cataldo R.
;
Poehls L.B.
;
Marcon C.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
network routing;
network-on-chip;
3D mesh network-on-chip;
efficient router architectures;
fast packet switching;
network architecture;
single cycle router;
Clocks;
Ports (Computers);
Routing;
Switches;
Three-dimensional displays;
Throughput;
Traffic control;
3D mesh NoC;
arbitration;
area consumption;
latency;
routing;
throughput;
78.
Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping
机译:
不确定性在线程映射软硬件仿真中的作用
作者:
Salvador G.
;
Nilakantan S.
;
Taskin B.
;
Hempstead M.
;
More A.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
Monte Carlo methods;
multi-threading;
search engines;
Google PageRank;
Monte Carlo design space exploration;
Sniper 5.3;
cycle-accurate simulation;
cycle-accurate simulator;
hardware simulation;
multithreaded programs;
multithreaded simulator;
program simulation;
simulation performance trade-off;
software simulation;
static thread mapping approach;
Aggregates;
Benchmark testing;
Hardware;
Instruction sets;
Monte Carlo methods;
Space exploration;
79.
Micro-architectural Enhancements in Distributed Memory CGRAs for LU and QR Factorizations
机译:
用于LU和QR分解的分布式内存CGRA中的微体系结构增强
作者:
Merchant F.
;
Maity A.
;
Mahadurkar M.
;
Vatwani K.
;
Munje I.
;
Krishna M.
;
Nalesh S.
;
Gopalan N.
;
Raha S.
;
Nandy S.K.
;
Narayan R.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
matrix decomposition;
memory architecture;
network-on-chip;
LU factorizations;
QR factorizations;
augmented reality;
coarse grained reconfigurable architectures;
computational fluid dynamics;
compute bound kernels;
core kernels;
distributed memory CGRA;
high performance computing platforms;
matrix multiplication;
microarchitectural enhancements;
network-on-chip;
Acceleration;
Bandwidth;
Clocks;
Computer architecture;
Linear algebra;
Registers;
US Department of Transportation;
computation;
numerical linear algebra;
parallelism;
reconfigurable architectures;
80.
Monitoring AMS Simulation: From Assertions to Features
机译:
监控AMS仿真:从断言到功能
作者:
Ain A.
;
Dasgupta P.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
analogue integrated circuits;
integrated circuit design;
mixed analogue-digital integrated circuits;
AMS simulation;
analog mixed-signal designs;
behavioral signatures;
feature definitions;
standard simulation platforms;
Battery chargers;
Computational modeling;
Frequency-domain analysis;
Hardware design languages;
Integrated circuit modeling;
Monitoring;
RLC circuits;
81.
BDD-Based Synthesis for All-Optical Mach-Zehnder Interferometer Circuits
机译:
基于BDD的全光马赫曾德尔干涉仪电路综合
作者:
Schonborn E.
;
Datta K.
;
Wille R.
;
Sengupta I.
;
Rahaman H.
;
Drechsler R.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
Boolean functions;
Mach-Zehnder interferometers;
VLSI;
adders;
binary decision diagrams;
multiplexing equipment;
optical interconnections;
semiconductor optical amplifiers;
BDD-based synthesis;
Boolean functions;
MZI;
Mach-Zehnder Interferometer switches;
SOA;
all-optical Mach-Zehnder interferometer circuits;
binary decision diagrams;
linear-time algorithm;
optical building blocks;
optical interconnects;
semiconductor optical amplifiers;
Boolean functions;
Data structures;
Libraries;
Logic gates;
Optical interconnections;
Optical interferometry;
Optical switches;
82.
Sensitivity Analysis Based Predictive Modeling for MPSoC Performance and Energy Estimation
机译:
基于灵敏度分析的MPSoC性能和能量估计的预测模型
作者:
Hongwei Wang
;
Ziyuan Zhu
;
Jinglin Shi
;
Yongtao Su
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
embedded systems;
multiprocessing systems;
regression analysis;
sensitivity analysis;
splines (mathematics);
system-on-chip;
ACOSSO regression based sensitivity analysis technique;
ACOSSO regression model;
L1-norm penalized least squares fitting problem;
MPSoC performance;
RCS modeling;
adaptive component selection;
architectural design space;
embedded processor architectures;
energy estimation problem;
global sensitivity analysis;
input variable selection;
model computing;
multiprocessor system on chip;
predictive modeling methods;
restricted cubic splines;
smoothing operator;
stepwise regression modeling technique;
Analytical models;
Computational modeling;
Computer architecture;
Estimation;
Input variables;
Predictive models;
Sensitivity analysis;
MPSoC;
energy;
performance;
predictive model;
sensitivity analysis;
83.
Thermal-Aware Application Scheduling on Device-Heterogeneous Embedded Architectures
机译:
设备异构嵌入式体系结构上的热感知应用调度
作者:
Swaminathan K.
;
Kotra J.
;
Huichu Liu
;
Sampson J.
;
Kandemir M.
;
Narayanan V.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
CMOS integrated circuits;
embedded systems;
field effect transistors;
multiprocessing systems;
power aware computing;
scheduling;
Power Wall;
device-heterogeneous embedded architectures;
embedded processors;
heterogeneous CMOS-tunnel FET multicore;
instruction slack-based scheme;
microarchitecture-level heterogeneity;
mobile processors;
power density;
profiling based static assignment scheme;
thermal-aware application scheduling;
CMOS integrated circuits;
FinFETs;
Multicore processing;
Performance evaluation;
Program processors;
Semiconductor device modeling;
Silicon;
84.
NFC for Pervasive Healthcare Monitoring
机译:
NFC适用于广泛的医疗保健监控
作者:
Prabhakar T.V.
;
Mysore U.
;
Saini U.
;
Vinoy K.J.
;
Amruthur B.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
biomedical communication;
near-field communication;
overvoltage protection;
patient monitoring;
thermometers;
NFC based battery charger circuit;
NFC based battery-less medical grade thermometer;
NFC power source;
android App;
near field communication;
overvoltage protection;
pervasive healthcare monitoring;
power 13 mW to 15 mW;
undervoltage protection;
wearable sensor devices;
wireless communication;
Batteries;
Coils;
Couplings;
Inductance;
Monitoring;
Smart phones;
Spirals;
85.
Optimized Logarithmic Barrel Shifter in Reversible Logic Synthesis
机译:
可逆逻辑综合中的优化对数桶式移位器
作者:
Mitra S.K.
;
Chowdhury A.R.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
arithmetic;
fault tolerant computing;
logic gates;
network synthesis;
optimisation;
shift registers;
threshold elements;
bidirectional arithmetic;
fault tolerance capability;
logarithmic barrel shifter optimization;
logical shifting;
reversible gates;
reversible logic synthesis;
rotate operation;
Bidirectional control;
Complexity theory;
Delays;
Fault tolerance;
Fault tolerant systems;
Hardware;
Logic gates;
Ancilla Inputs;
Delay;
Garbage Outputs;
Quantum Cost;
86.
Low-Area and Low-Power Reconfigurable Architecture for Convolution-Based 1-D DWT Using 9/7 and 5/3 Filters
机译:
使用9/7和5/3滤波器的基于卷积的一维DWT的低面积,低功耗可重配置架构
作者:
Meher P.K.
;
Mohanty B.K.
;
Swamy M.M.S.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
adders;
application specific integrated circuits;
convolution;
discrete wavelet transforms;
distributed arithmetic;
high-pass filters;
low-pass filters;
low-power electronics;
reconfigurable architectures;
shift registers;
5-3 filters;
9-7 filters;
ADP;
ASIC synthesis;
DA-based structure design;
EPO;
MUX;
adder-based formulation design optimization;
bit-shift minimization;
clock cycle;
complexity overhead;
convolution-based 1-D DWT;
discrete wavelet transform;
distributed arithmetic;
hardwired-shifters;
high-pass filter;
higher usable frequency;
intermediate bit-width reduction;
low-area reconfigurable structure architecture;
low-pass filter;
low-power reconfigurable structure architecture;
multiplier-based structure design;
registers;
two-stage pipeline structure implementation;
Adders;
Clocks;
Discrete wavelet transforms;
Periodic structures;
Pipeline processing;
Registers;
Throughput;
Discrete Wavelet Transform;
VLSI;
low-pwer design;
87.
Using Boolean Tests to Improve Detection of Transistor Stuck-Open Faults in CMOS Digital Logic Circuits
机译:
使用布尔测试来改善对CMOS数字逻辑电路中晶体管卡塞开路故障的检测
作者:
Xijiang Lin
;
Reddy S.M.
;
Rajski J.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
CMOS logic circuits;
automatic test pattern generation;
fault diagnosis;
logic testing;
Boolean tests;
CMOS digital logic circuits;
ISCAS-89 benchmark circuits;
TSOP faults;
faulty gate;
glitches;
hazard-based initialization;
initialization pattern;
redundant gates;
steady state Boolean analysis;
stuck-at fault;
test generation procedures;
transient analysis;
transistor stuck-open faults;
two-pattern tests;
Circuit faults;
Delays;
Fault detection;
Hazards;
Logic gates;
Transient analysis;
Transistors;
Transistor stuck open faults;
fault detection tests;
multi-cycle tests;
88.
Ultra-fast Cap-less LDO for Dual Lane USB in 28FDSOI
机译:
适用于28FDSOI双通道USB的超快速无电容LDO
作者:
Singh S.K.
;
Kanungo G.D.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
peripheral interfaces;
phase locked loops;
silicon-on-insulator;
voltage regulators;
28FDSOI;
MOS current;
PLL;
current 15 mA;
dominant output pole;
dual lane USB core;
low dropout regulator;
on-chip capacitance density;
reference generator;
ultrafast capacitor-less LDO;
voltage 1 V;
voltage 1.6 V;
voltage regulators;
Capacitance;
Capacitors;
Logic gates;
Regulators;
System-on-chip;
Transient analysis;
Universal Serial Bus;
CMOS;
FDSOI;
LDO;
PSRR;
fully on-chip voltage regulators;
linear voltage regulators;
voltage regulators;
89.
Thermal Extension of the Total Bandwidth Server
机译:
总带宽服务器的热扩展
作者:
Ahmed R.
;
Bansal A.
;
Kakunoori B.
;
Ramanathan P.
;
Saluja K.K.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
processor scheduling;
real-time systems;
T2BS;
deadline constraint;
external event;
internal event;
periodic task timing constraint;
response time analysis;
system thermal constraint;
thermal extension;
thermally constrained hard real-time system;
total bandwidth server;
Bandwidth;
Computational modeling;
Mathematical model;
Power demand;
Schedules;
Servers;
Time factors;
Real-time systems;
thermal constrained scheduling;
total bandwidth server;
90.
Formal Methods for Pattern Based Reliability Analysis in Embedded Systems
机译:
嵌入式系统中基于模式的可靠性分析的形式化方法
作者:
Ghosh S.
;
Dasgupta P.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
embedded systems;
fault tolerant computing;
formal verification;
software reliability;
temporal logic;
embedded systems;
fault distribution;
formal methods;
formal verification;
omega-regular languages;
pattern based reliability analysis;
periodic tasks;
real time calculus specifications;
reliable execution;
reliable service guarantees;
service throughput;
Automata;
Computer network reliability;
Embedded systems;
Model checking;
Reliability engineering;
Throughput;
91.
EvoDeb: Debugging Evolving Hardware Designs
机译:
EvoDeb:调试不断发展的硬件设计
作者:
Bhattacharjee D.
;
Banerjee A.
;
Chattopadhyay A.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
configuration management;
digital systems;
formal verification;
program debugging;
EvoDeb;
automated design verification;
comprehensive design verification;
debugging evolving hardware designs;
design complexity;
fabrication costs;
hardware configuration management tools;
hardware design code-bases;
modern digital systems;
open-source hardware designs;
silicon respins;
software configuration management;
Clocks;
Computer bugs;
Debugging;
Hardware;
Hardware design languages;
Sensitivity;
Time-domain analysis;
92.
New Methods for Simulation Speed-up and Test Qualification with Analog Fault Simulation
机译:
模拟故障仿真的仿真加速和测试资格验证的新方法
作者:
Devanathan V.R.
;
Balasubramanian L.
;
Parekhji R.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
analogue circuits;
electronic design automation;
fault simulation;
mixed analogue-digital integrated circuits;
system-on-chip;
SOC requirements;
analog EDA tools;
analog fault simulation;
analog-digital interface;
design verification test bench;
embedded processing;
mixed-signal SOC;
regular fault simulation;
simulation speed-up;
smart model management;
specification based tests;
test qualification;
Accuracy;
Analog circuits;
Automatic test pattern generation;
Circuit faults;
IP networks;
SPICE;
System-on-chip;
Analog DFT and test;
analog fault simulation;
test optimisations for analog circuits;
93.
Mode-Division-Multiplexed Photonic Router for High Performance Network-on-Chip
机译:
模分多路复用光子路由器,用于高性能片上网络
作者:
Dang D.
;
Patra B.
;
Mahapatra R.
;
Fiers M.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
integrated optics;
low-power electronics;
micromechanical resonators;
network-on-chip;
optical waveguides;
power consumption;
time division multiplexing;
wavelength division multiplexing;
MDM scheme;
MRR;
TDM;
WDM;
communication bandwidth;
high performance 5×5 photonic router design;
high performance network-on-chip;
high-performance electronic router;
insertion loss;
low power 5×5 photonic router design;
metallic interconnects;
mode-division-multiplexed photonic router;
multimodal communication;
nonblocking 5×5 photonic router design;
photonic NoC;
power consumption;
silicon microring resonators;
silicon-waveguides;
size 45 nm;
time-division-multiplexing;
Optical crosstalk;
Optical losses;
Optical switches;
Optical waveguides;
Photonics;
Power demand;
Waveguide lasers;
Network-on-chip;
mode-division-multiplexing;
non-blocking;
photonic;
waveguide;
94.
SPAA-Aware 2D Gaussian Smoothing Filter Design Using Efficient Approximation Techniques
机译:
使用高效逼近技术的SPAA感知2D高斯平滑滤波器设计
作者:
Jaiswal A.
;
Garg B.
;
Kaushal V.
;
Sharma G.K.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
Gaussian processes;
approximation theory;
edge detection;
smoothing methods;
SPAA metric;
SPAA-aware 2D Gaussian smoothing filter design;
approximation technique;
edge detection;
energy-efficient approximate 2D GSF architecture;
energy-efficient approximate 2D Gaussian smoothing filter architecture;
energy-efficient designs;
limited battery lifetime;
nearest pixel approximation;
portable multimedia devices;
rounding-off Gaussian kernel coefficient;
speed-power-area-accuracy;
Adders;
Approximation methods;
Complexity theory;
Computer architecture;
Image edge detection;
Kernel;
Smoothing methods;
Approximate design;
Edge-detection;
Energy-efficiency;
Error Tolerant Applications;
Gaussian Smoothing Filter;
95.
Statistical Analysis of 64Mb SRAM for Optimizing Yield and Write Performance
机译:
用于优化良率和写入性能的64Mb SRAM的统计分析
作者:
Narang G.
;
Sharma P.
;
Jain M.
;
Grover A.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
SRAM chips;
design of experiments;
integrated circuit design;
integrated circuit modelling;
integrated circuit yield;
statistical analysis;
system-on-chip;
6T SRAM cell;
DFY analysis;
DoE method;
SRAM cell performance;
SRAM designer;
design-for-yield analysis;
design-of-experiments;
device variation;
die area;
high-performance SoC;
nonlinear model;
performance-yield trade-off;
size 65 nm;
statistical analysis;
time 573 ps;
time 656 ps;
variation estimation;
write performance;
write time sensitivity estimation;
write time specification;
write-time model;
yield optimization;
Analytical models;
Probability;
SRAM cells;
Sensitivity;
Solid modeling;
System-on-chip;
6T SRAM cell;
Bivariate analysis;
Design for yield (DFY);
Design of Experiment (DoE);
Nonlinear Regression;
Write Speed;
96.
Cross-Layer Exploration of Heterogeneous Multicore Processor Configurations
机译:
异构多核处理器配置的跨层探索
作者:
Sarma S.
;
Dutt N.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
energy conservation;
evolutionary computation;
multiprocessing systems;
power aware computing;
HMP configuration;
area-power budget;
chip area;
core types;
cross-layer exploration;
design stages;
die area;
energy efficiency;
evolutionary optimization framework;
hardware architecture;
heterogeneous multicore processor configurations;
homogenous multiprocessors;
operating system;
optimization problem;
predictive cross-layer approach;
system level constraints;
task allocation strategies;
verification stages;
Benchmark testing;
Hardware;
Multicore processing;
Predictive models;
Radiation detectors;
Resource management;
Cross-Layer Design;
Design Space Exploration;
Heterogeneous multicore processor;
Multi-Processor Systems-on-Chip;
Task Allocation and Scheduling;
97.
Framework for Selective Flip-Flop Replacement for Soft Error Mitigation
机译:
用于软错误缓解的选择性触发器替换框架
作者:
Torvi P.V.
;
Devanathan V.R.
;
Kamakoti V.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
flip-flops;
logic circuits;
microprocessor chips;
optimisation;
radiation hardening (electronics);
DICE;
automotive electronics;
aviation electronics;
cell library;
dual interlocked storage cells;
failure-in-time rate;
industrial IP core;
linear optimization problem;
selective flip-flop replacement;
soft error mitigation;
standard master-slave flip-flops;
Clocks;
Computational modeling;
Integrated circuit modeling;
Latches;
Silicon;
Standards;
Transient analysis;
soft error mitigation;
98.
Few Good Frequencies for Power-Constrained Test
机译:
功率受限测试的频率很少
作者:
Gunasekar S.
;
Agrawal V.D.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
VLSI;
approximation theory;
clocks;
integrated circuit testing;
piecewise linear techniques;
search problems;
system-on-chip;
test equipment;
LES algorihm;
kth-root solution;
locally exhaustive search algorithm;
optimum clock periods;
periodic clock testing method;
piecewise linear approximation;
power estimation;
power-constrained test;
pseudoenergy profile;
test cycles;
test equipment;
test program;
test time reduction;
timing analysis tools;
Clocks;
Delays;
Linear approximation;
Power demand;
Synchronization;
Testing;
Vectors;
Aperiodic testing;
digital test;
test power;
test time;
99.
Power Optimization Techniques for DDR3 SDRAM
机译:
DDR3 SDRAM的电源优化技术
作者:
Panda P.R.
;
Patel V.
;
Shah P.
;
Sharma N.
;
Srinivasan V.
;
Sarma D.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
DRAM chips;
low-power electronics;
optimisation;
queueing theory;
DDR3 SDRAM;
adaptive threshold technique;
low power SELF-REFRESH operating mode;
memory controller;
memory power optimization technique;
power consumption;
power management technique;
queue-resizing optimization;
Benchmark testing;
Memory management;
Optimization;
Power demand;
SDRAM;
Switches;
100.
Parameterizable FPGA Framework for Particle Filter Based Object Tracking in Video
机译:
用于视频中基于粒子滤波的对象跟踪的可参数化FPGA框架
作者:
Engineer P.
;
Velmurugan R.
;
Patkar S.
会议名称:
《International Conference on VLSI Design;International Conference on Embedded Systems Design》
|
2015年
关键词:
computational complexity;
field programmable gate arrays;
image sequences;
object tracking;
particle filtering (numerical methods);
FPGA framework;
color video sequence;
computational complexity;
embedded platform;
image sequences;
particle filter based object tracking algorithm;
resource usage;
Clocks;
Field programmable gate arrays;
Hardware;
Histograms;
Image color analysis;
Object tracking;
Random access memory;
FPGA;
Object tracking;
Particle filter;
Smart camera;
framework;
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