Memory access performance is strongly dependent on the processing sequence of memory transactions. On a system bus, the outstanding memory transactions issued by a bus device often have consecutive address and the same read or write (R/W) types. Under traditional bus arbitration schemesi however, outstanding transactions from different devices are most likely to be interleaved with each other, which incurs non-sequential addressing access as well as different R/W types access. Due to the limited scheduling performance of the memory controller, such sequences usually prevent the memory controller from accessing the memory effectively. In this paper, we propose a novel bus arbitration scheme, CGH, to minimize the number of memory row addressing and R/W type context switches. CGH can recognize and grant outstanding transaction sequence from the same bus device with the same row address and R/W type. It also prioritizes the requests which have the same memory row address and R/W type as the most recent transaction during grant handoff to achieve further improvement. Being applied to the PKUnity-SK SoC, the proposed arbitration scheme significantly elevates the memory access performance by 21, 37% with only 2. 83% area overhead. It also reduces the memory power consumption by 15. 15% because of less row activations.%访存交易的处理顺序对内存访问的性能有重要影响.同一个SoC设备发出的多个未决交易往往地址连续且读写类型相同.然而,传统的总线仲裁方法导致各个设备发出的未决交易序列交错地发送至内存控制器,而内存控制器访存调度的范围有限,最终导致此类序列通常无法连续地访问内存.为解决此问题,提出一种新型的总线仲裁方法CGH,该方法利用SoC设备通信行为的特征,通过识别同一个SoC设备发出的、行地址和读写类型相同的未决交易序列并让其连续获得仲裁授权,减少内存切换行地址和读写类型的次数；同时,在选择将要授权的未决交易序列时,优先考虑行地址和读写类型与最近授权交易相同的申请,进一步提高访存效率,将CGH仲裁方法应用至北大众志-SK SoC后,系统访存性能提高了21.37％,而总线面积仅增加2.83％.此外,由于行地址切换次数减少,内存的能耗也降低了15.15％.
展开▼
