基于FPGA和DDR3 SDRAM的大规模查找表设计与实现

摘要

For the wide requirements of high speed large capacity data reading and writing,a new method was proposed,which used FPGA control DDR3 SDRAM to realize large-scale high-speed lookup table.This method used Altera's Cyclone V family FPGA to complete the DDR3 SDRAM control.In the Quartus Ⅱ development environment used Verilog HDL was used to describe the various timing of DDR3 SDRAM state machine to achieve aDDR3 SDRAM controller.A test platform was set up for testing and the SignalTap Ⅱ logic analyzer used to test and regulate the controller's working flow.Eventually the results indicate that the controller accuracy of looking up accurately and the speed of looking up reach 40 Mtime per second.%针对高速大容量数据读写的广泛需求,提出一种FPGA控制DDR3 SDRAM实现大规模高速查找表的方法.该方法采用Altera公司Cyclone V系列的 FPGA,在Quartus Ⅱ开发环境下,利用Verilog HDL编程语言,通过状态机来描述对DDR3 SDRAM的各种时序操作,设计了用户自定义DDR3 SDRAM控制器.搭建了测试系统进行测试,同时使用SignalTap Ⅱ逻辑分析仪对控制器的工作流程进行了调试和验证.最终测试结果表明,查表准确且速度达到了40 M次/s.