A digital baseband-processor for UHF RFID tags was designed and implemented in this study based on the EPCTM class-1 generation-2 (C1G2) UHF RFID protocol to realize the digital system' s ultra low power consumption under the prerequisite of ensuring the protocol' s functions. The low-power consumption techniques, such as system clock programming, state optimization coding, global gating asynchronous counter, gate-level power optimization, operand isolation, were introduced into the design and the final power consumption of 13. 8 μW of the baseband was achieved. In order to achieve the goal of Anti-Collision, an oscillator-based random number generator was designed, and its power was controlled to less than 2μW. The chip was fabricated in the Chartered 0. 18μm standard CMOS process. The die area of the baseband was only 482 μm ×480μm. The test results of the chip were basically consistent with the simulation results.%依据EPC C1G2协议设计了一种用于无源UHF射频识别RFID标签芯片的数字基带电路,在完成协议规定功能的前提下实现了系统的低功耗.通过引入系统时钟规划、状态优化编码、全局钟控、异步计数器、门级功耗优化与操作数隔离等多种低功耗技术,设计最终功耗为13.8μW.为更好地实现系统的防冲突,采用了一种基于振荡器采样的真实随机数产生器,整个随机数产生电路功耗控制在2μW以内.设计采用Chartered0.18μm工艺实现,数字电路面积为482μm×480μm,芯片测试结果与仿真结果基本符合.
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