一种应用于纳米工艺存储编译器的高效且精确例化功耗表征方法

摘要

Power consumption plays a major factor on the performance of nano-meter designs. For a typical SoC design with tens of million gates, the area of memory is most likely to occupy over half of the chip size. In addition to applying the low power design techniques to chip design, an efi~cient and accurate power characterization method for both static and dynamic power is very important to enable the design budgeting, especially for portable applications. In this paper, we will review the traditional method and its limitation and present a new method which not only solves previous bottleneck but also retains the accuracy. The layout-dependent effects on devices and wire parasitic in nano-meter technology are considered for accuracy requirement. The implementation flow is illustrated and results are shared as reference.%随着芯片规模的不断增大，功耗成为影响纳米工艺芯片设计性能的主要因素。而在一个典型的千万门级规模SoC设计中，存储器的面积往往占到整个芯片面积的一半以上!因此，除了在实际的芯片设计中实现低功耗设计方法，一种高效准确的对静态和动态功耗的表征方法对于进行设计的功耗预估是非常重要的，尤其是对于便携式应用的芯片项目。在这篇论文中，我们在回顾传统功耗表征方法和其应用限制的同时，将阐述一种不仅可以解决当前功耗表征瓶颈而且具有高准确度的方法。为了达到高精度的设计要求，我们将纳入在纳米工艺下布图相关效应对器件和连线的寄生参数的影响。在文章中我们解释了这种方法的实现流程，并将一些实验结果分享提供读者参考。