Fixed and reconfigurable, fully integrated, switching power supplies for dynamic loads.

摘要

The ever present trend to provide faster computation for less power has been one of the most important drivers of the semiconductor industry. From device engineering where balancing dynamic and leakage power is the key tradeoff, to high-level operating system task scheduling, the goal is always to increase efficiency without sacrificing performance. The recent shift to multicore processors makes the power optimization of the system more relevant than ever. In addition, attempts to bring voltage regulation on chip allow for dynamical power management on short time scales not possible before. This work explores the challenging design space of fully integrated, step-down voltage conversion and regulation. To reduce complexity and area overheads, one approach is to group cores (loads) in independent voltage domains and power them with a relatively large, inductor-based converter. To this end, a 3-level buck-type design is presented with efficiency improvements at low current loads to enable efficient operation in extended sleep states. To achieve per-core supply voltage control, relatively small switched capacitor converters are explored. Considered individually, these converters need to be over-provisioned for the worst case load scenario. However, substantial area savings can be achieved by dynamically reallocating capacitance to supply power to the most demanding cores/loads. In addition to 40% area savings, further exploration reveals order of magnitude better transient response and better efficiency at low power for these Reconfigurable Power Distribution Networks.