Power scalable and low power design techniques for pipeline ADCs.

摘要

The proliferation of portable electronic devices with high data-rate wireless communication capabilities and the increasing emphasis on energy efficiency is continuously applying pressure on the performance and power consumption of ADCs and other mixed-signal systems. Research on increasing the power efficiency of pipeline ADCs, which are popular for their high resolution and speed capabilities, has focused on power scalability and mixed-signal power reduction techniques such as opamp-sharing. This dissertation presents the research and development of both a linear power scalable technique for implementing scalable pipeline ADCs and a Current-Reuse OTA topology that facilitates opamp-sharing in low power pipeline ADCs.;A power scalable 12b pipeline ADC implemented by enabling or disabling MDAC OTAs in parallel is presented. Power scaling is achieved without varying the DC bias conditions of critical analog nodes, reducing design complexity and allowing an existing design to be rapidly reconfigured for new specifications. The ADC can be designed for optimal power consumption over the entire sampling rate range due to linear power scaling provided by the parallel OTA approach. The proposed ADC operates over a sampling rate range of 20MS/s to 40MS/s with >62dB SNDR. The analog power varies linearly from 36mW at 20MS/s to 72mW at 40MS/s. The ADC was fabricated in 0.18microm CMOS process and occupies a die area of 1.9mm2.;A 10b opamp-sharing pipeline ADC using Current-Reuse OTAs with dual NMOS differential inputs is presented. The current-reuse OTA topology facilitates opamp-sharing between all of the consecutive pipeline stages, minimizing power consumption and die area. Analog transistors in the OTA are always biased in saturation ensuring no loss of settling time due to OTA power turn-on delays. The ADC is fabricated in a 0.18microm CMOS process and occupies an active die area of 0.7mm2 At 50MS/s, maximum SNDR of 58dB (ENOB=9.3b) is achieved with 9.2mW analog power consumption on a 1.8V supply.