The clock and data recovery (CDR) circuit is a key enabling block in modern high speed serial communication systems with applications covering a wide range from wireline long-haul networks to chip-to-chip and backplane communications. Most high-speed CDR circuits employ bang-bang phase detectors for their simple structure and high speed of operation, unlike linear phase detectors. The bang-bang phase detector has two outputs indicating the sign of the phase detector. The two outputs cause the behaviour of the loop to be nonlinear resulting in a difficult analysis.;As the bang-bang CDR circuit became the most popular choice for designers, there was a need for accurate modeling of the loop relating jitter characteristics to design parameters. While there are many methods presented recently for analyzing bang-bang CDR circuits, in our analysis we will focus on two major methods and use them throughout the thesis. Jitter transfer, as one of the figure of merits of a CDR, is defined and analyzed, followed by the derivation of a more accurate expression that complies with the definition. A second figure of merit, jitter tolerance, is investigated in considerable depth using mathematical tools to simplify the analysis. A simpler expression for jitter tolerance is proposed and compared with existing expressions by means of behavioural simulations. Novel analysis explains the behaviour of the loop in different regions of the jitter tolerance curve.
展开▼
