Low power, low phase noise CMOS ring oscillators.

摘要

The system-on-a-chip (SOC) movement demands increasingly greater levels of integration. In an effort to reduce part count, traditional implementations are being abandoned for integrated solutions. This presents numerous problems for wireless circuits. Radio frequency transceivers in particular consist of a veritable collage of incompatible technologies. For example, high efficiency power amplifiers are typically fabricated in alternative, high mobility semiconductors. High-Q resonators have also been traditionally implemented in a non-monolithic fashion, either with crystals or discrete inductors and capacitors. Efforts to move these components on chip have found some success but at a cost of large area consumption and reduced Q. Current research has focused on ring oscillators as an alternative approach. Historically, due to their poor noise performance, ring oscillators have found use only in low frequency applications such as clock recovery and skew reduction. Because of their relatively small footprint and ease of integration, efforts to improve ring oscillator noise performance have renewed.; This work contributes to complimentary metal-oxide-semiconductor (CMOS) ring oscillator design in several ways. First, an in-depth study of CMOS ring oscillator functionality and noise theory is provided. Second, from this discussion, noise minimizing design techniques are identified and a new Dual-Inverter Ring Oscillator (DIRO) is proposed. Third, in order to provide an accurate comparison between the new architecture and prior art, two other established ring oscillator topologies have been fabricated concurrently. This experiment eliminates any possibility of a process advantage. Each of these ring oscillators is comprehensively characterized in terms of intrinsic phase noise, power supply rejection and common mode rejection.; All ring oscillators were fabricated in a 0.18μm, 5-metal CMOS process. The proposed design has a measured frequency range of 650MHz–1040MHz using a supply voltage of 2.0V. The phase noise performance of the 2-stage DIRO oscillator at f_osc = 913MHZ @600KHz offset is −16.55dBc/Hz while drawing 18.95mW.