Technology scaling has brought the IC industry to the point where several distinct components can be integrated onto a single chip. Many of these System-on-a-Chip (SoC) devices would benefit from the inclusion of reprogrammable logic on the silicon die, as it can add general computing ability, provide run-time reconfigurability, or be used for post-fabrication modifications. Also, by tailoring the reconfigurable fabric to the SoC domain, additional area/delay/power gains can be achieved over current, more general fabrics. Developing a domain-specific reconfigurable fabric has traditionally taken too much time and effort to be worthwhile. We are alleviating these design costs by automating the process of creating domain-specific reconfigurable fabrics: a project we call Totem.; This dissertation details our work in creating tools that will automate the creation of domain-specific PLAs, PALs, and CPLDs for use in SoC devices. The input to the toolset is a group of circuits that need to be supported on the reconfigurable fabric. The tools then create a PLA, PAL, or CPLD that is tailored to the specific test circuits, with an option for strategically providing additional resources in order to support future, unknown circuits. The output of the toolset is a fully optimized VLSI layout of the reconfigurable fabric. This VLSI layout can be provided to a designer for direct integration into an SoC design.; Our domain-specific CPLD architectures based on full crossbars outperform representative fixed architectures by 5.6x to 11.9x in terms of area-delay product. Our toolset has also been used to find several more efficient fixed architectures, but our domain-specific architectures still outperform these new fixed architectures by 1.8x to 2.5x. Sparse-crossbar-based CPLDs have also been created, and require only 37% of the area and 30% of the propagation delay of the full-crossbar-based CPLDs. Lastly, an analysis of our sparse-crossbar-based CPLD architectures suggests that, in order to support future circuits, the crossbar switch density should be augmented by 5% over the base density, and additional PLAs of the base PLA-size should be provided for additional logic utilization.
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