A high-troughput radix-4 log-MAP decoder with low complexity LLR architecture

摘要

The throughput of turbo decoder is limited by the recursion architecture. In this paper, an improved radix-4 recursion architecture is presented. In order to decrease the critical path delay, a hybrid 4-inputs addition/subtraction structure is employed. Moreover, we present a modified trace-back architecture to decrease the hardware complexity of the log-likelihood ratios (LLR) architecture. The area of the proposed MAP decoder is 0.58 mm² on UMC 0.13 mum standard cell technology and under the worst case a maximum throughput of 600 Mbps can be achieved.