首页> 外文会议>Tenth European Solid-State Circuits Conference (ESSCIRC '84) >A 4 Byte 18 Ns ECC for Hard and Soft Correction
【24h】

A 4 Byte 18 Ns ECC for Hard and Soft Correction

机译:用于硬和软校正的4字节18 Ns ECC

获取原文
获取原文并翻译 | 示例

摘要

The constant increase of memory size and the search for improving the reliability in the recent computers have led to introduce a certain amount of hardware redundancy in an attempt to improve the Mean Time Between Failure. The memory part has received a special attention because of the amount of hardware involved making the memory a large contributor to the total failure rate of the machine. The situation is worse with the use of the high density Random Access Memory modules subject to the so-called "soft error". A phenomenon due, among other things, to the residual radio activity of the materials used to build the module itself energy of which is sometimes sufficient to alter the contents of the very low capacitor, typically 50 to 70 femtoFarad, that serves as memory element.
机译:存储器大小的不断增加以及最近计算机中对提高可靠性的追求已导致引入一定数量的硬件冗余,以尝试改善平均故障间隔时间。由于涉及的硬件数量使内存成为机器总体故障率的重要因素,因此内存部分受到了特别的关注。使用高密度随机存取存储器模块会导致所谓的“软错误”,情况会更糟。除其他因素外,由于用于构建模块本身的材料的残留放射性而引起的现象,其能量有时足以改变用作存储元件的非常低的电容器(通常为50至70毫微微法拉)的电容。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号