Nano-CMOS circuit design and performance evaluation by inclusion of ballistic transport processes

摘要

The scaling of channel length and width in a nanoscale n-type MOSFET (NMOS) and p-type MOSFET (PMOS) is examined in ballistic (B) nano-CMOS design. The ballistic process is predominant in a nanoscale device when channel length is shorter than the mean free path. Our predictive model agrees well with 45nm experimental data from IBM. It is shown that the mobility is lower in the short channel device compared to the mobility in the long channel device due to the ballistic process.