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Nature of Interface Traps in Si/SiO_2/HfO_2 /TiN Gate Stacks and its Correlation with the Flat-Band Voltage Roll-Of

机译:Si / SiO_2 / HfO_2 / TiN栅堆叠中界面陷阱的性质及其与平带电压滚降的关系

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摘要

We have carried out a detailed experimental investigation of the trap parameters - trap energy, trap density, and hole capture cross-section - in a large number of p-Si/SiO_2/HfO_2/TaN MOS capacitors fabricated on wafers with graded SiO_2 layer, and of the flat-band voltage, using a newly developed admittance spectroscopy technique, which yields accurate values of the surface potential and the flat-band voltage, and makes use of the measured conductance to obtain accurate values of the trap parameters. The correlation, if any, between the trap density and the flat-band voltage has been analyzed.
机译:我们对在具有渐变SiO_2层的晶片上制造的大量p-Si / SiO_2 / HfO_2 / TaN MOS电容器中的陷阱参数-陷阱能量,陷阱密度和空穴俘获截面进行了详细的实验研究,通过使用新开发的导纳光谱技术,获得平坦的表面电势和平坦带电压的准确值,并利用测得的电导来获得陷阱参数的精确值。已经分析了陷阱密度和平带电压之间的相关性(如果有)。

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