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Progress towards Optical Interconnects for Intrachip Global Communication

机译:面向芯片内全球通信的光互连技术的进展

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Microprocessor performance is now limited by the poor delay and bandwidth performance of the on-chip global wiring layers. Although relatively few in number, the global metal wires have proven to be the primary cause of performance limitations - effectively leading to a premature saturation of Moore's Law scaling in future Silicon generations. Building upon device-, circuit-, system- and architectural-level models, a framework for performance evaluation of global wires is developed aimed at quantifying the major challenges faced by intrachip global communications over the span of six technology generations. This paper reviews the status of possible intra-chip optical interconnect solutions in which the Silicon chip's global metal wiring layers are replaced with a high-density guided-wave or free-space optical interconnection fabric. The overall goal is to provide a scalable approach that is compatible with established silicon chip fabrication and packaging technology, and which can extend the reach of Moore's Law for many generations to come. To achieve the required densities, the integrated sources are envisioned to be modulators that are optically powered by off-chip sources. Structures for coupling dense modulator arrays to optical power sources and to free-space or guide-wave optical global fabrics are analyzed. Results of proof-of-concept experiments, which demonstrate the potential benefits of ultra-high-density optical interconnection fabrics for intra-chip global communications, are presented.
机译:现在,微处理器性能受到片上全局布线层较差的延迟和带宽性能的限制。尽管数量相对较少,但全球金属线已被证明是性能受限的主要原因-有效地导致了摩尔定律在未来的硅世代中过早饱和。建立在设备,电路,系统和体系结构级别的模型的基础上,开发了一种用于评估全局布线性能的框架,旨在量化六代技术跨时代的芯片内全局通信所面临的主要挑战。本文回顾了可能的芯片内光学互连解决方案的现状,在这些解决方案中,硅芯片的全局金属布线层已被高密度波导或自由空间光学互连结构所取代。总体目标是提供一种与现有的硅芯片制造和封装技术兼容的可扩展方法,并可以将摩尔定律的影响范围扩展到很多代。为了实现所需的密度,可以将集成源设想为由片外源进行光供电的调制器。分析了将密集调制器阵列耦合到光电源以及自由空间或波导光学全局结构的结构。提出了概念验证实验的结果,这些结果证明了超高密度光学互连结构对于芯片内全球通信的潜在好处。

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