A Power-on Reset Circuit for HVIC Targeting for Resiliency against High Voltage Peak Noise

摘要

In HVIC (High Voltage Integrated Circuit) driving power semiconductor device, it is a crucial task tornprevent the driver output from being hauled up by power supply ramp-up at initial stage. For HVICrnapplications such as Fairchild SPM5, where HVICs drive the MOSFET devices, the PoR function impliesrnfar greater importance than IGBT driving counterparts, because they exploit relatively small bootstraprncapacitors. This paper describes a power-on reset circuit that is seamlessly interwoven with an extantrnUVLO (Under Voltage Lock Out) circuit, thereby adding minimal number of circuit elements. The designrnof the circuit carries a special concern about the robustness against high voltage peak noise, which isrnsevere especially on the high side DC link of the MOSFET-based inverter applications. The proposedrncircuit is implemented using the Fairchild HDG4D BCDMOS high voltage process, which has 680VrnLDMOS and 25V 1.2μm CMOS and BJT cells.