Mask Side wall clamping

摘要

Current state-of-the-art optical lithography scanners using 193nm wavelength lasers and numerical apertures of 1.35 have reached fundamental printing limits. Yet, consumer demands and device trends continue to drive smaller feature sizes, and most IC manufacturers have already navigated beyond the lithographic printing limits by turning to double patterning techniques. Requiring an extra lithography step for these techniques, it is essential to keep costs down by e.g. increasing wafer throughput. Currently, leading edge immersion scanners consistently produce over 190 wafers per hour (wph). However, to keep decreasing the cost per transistor, higher throughputs of 250 wph are key targets for the year 2013. Amongst others, higher throughput can be acquired by increasing acceleration of the positioning stages. One of the constraining technologies is the current mask or reticle clamping concept due to its friction based acceleration. While current reticle accelerations amount to 150 m/s~2, some research3 has already been performed to reticle stage accelerations of 400 m/s~2. In this paper, a novel reticle clamping concept is presented. The concept is shown to be suitable for accelerations larger than 400 m/s~2 entirely eliminating reticle slip, whilst meeting specifications for clamping induced error with a pattern deformation of ＜ 0.12 nm on wafer stage level (WS) and comprising high clamp stiffness.