Voiding, Cracking, and Debonding of Microelectronic Packaging and Interconnects

摘要

Modeling activities at Materials and Structures Laboratory of Florida Institute of Technology (FIT) are presented for analyzing the thermal-mechanical behavior, voiding, cracking and debonding existing inside microelectronic packaging and interconnects. The problems specifically discussed here are : 1) 3-D modeling of cracking and debonding for typical plastic packaging assemblies subjected to combined moisture and temperature loading, in which the mixed mode fracture and damage tolerant design is emphasized; 2) Axisymetric for transient response of a plastic package due to chip heating; 3) Void interaction modeling for creep response inside an idealized solder joint subjected to thermal cycling; 4) Plated through hole (PTH) cracking of printed circuit boards due to wave soldering and the effects of manufacturing defects on the reliability of the printed -circuit board (PCB); 5) Modeling of thermal stresses and voiding for fine metal lines and 6) Microindentation testing simulations for mechanical properties of deposited thin film substrate systems.