Test coverage models for system test?

摘要

In the world of IC testing, efficiency measurements are based on test coverage of modeled faults, often stuck at faults. While this has been effective at the chip level to improve the quality of chip testing, the question is how can this be transferred to the system test level? At the system level we are faced with several potential complications in measuring the quality of the test process. These include the fact that all of the chips have already been tested individually and tested again when they were put on the board. This previous testing leads to a vague fault spectrum and a non-random fault distribution. Do we count the supplier test coverage in the overall system test coverage? Multiple suppliers with different levels of test coverage and quality for the same component can also complicate the determination of test coverage. System configuration options can vary widely within one system type. These complexities need to be dealt with while keeping any test coverage analysis simple enough to explain to management and other stakeholders. The author will discuss two possible techniques to address these complications. In the first technique, we will look at what a comprehensive fault model may look like at the system level. The second technique involves a more traditional approach of implementing a test coverage analysis based on functional faults and Failure Mode Effect Analysis (FMEA).