Mixed-signal BIST: fact or fiction

摘要

Embedded test is essential for many of today's high-speed electronic designs that involve state-of-the-art silicon processes. Attempting to perform timing and frequency measurements across the chip I/O is fraught with parasitic interconnect issues leading to excessive noise pick-up, asymmetrical delays and uneven incident/reflection levels. Interesting enough, the problem of on-chip interconnect is a well-recognized problem of many VLSI-related conferences. Packing such large number of interconnects in such a small volume leads to numerous coupling and cross-talk phenomena that is limiting the performance of advance circuit designs. The problem associated with moving large volumes of data across the chip interface during the test phase seems to have gained less interest at leading conferences when in fact the problem is quite similar, if not worst.