On the design of efficient modulo 2n+1 multiply-add-add units

摘要

In this work efficient modulo 2n+1 fused multiply-add-add units for weighted and diminished-1 operands are proposed. The proposed architectures can be applied in systems in which fused multiply-add-add units accelerate the execution of the targeting algorithms. Long integer arithmetic would also show considerable gains by using multiply-add-add units. Also, implementation results for the proposed units are given and compared to the performance of existing designs.