A 5Gb/s Automatic Sub-Bit Between-Pair Skew Compensator for Parallel Data Communications in 0.13μm CMOS

摘要

A between-pair skew compensator for parallel data communications is presented. It can detect time skew between two independent data sequences using continuous-time correlations and then automatically align the two using a voltage controlled wide-bandwidth data delay line. A 5Gb/s sub-bit between-pair skew compensator in 0.13μm CMOS occupies 0.03mm active die area and dissipates 22.5mW.