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Reduced RTN Amplitude and Single Trap induced Variation for Ferroelectric FinFET by Substrate Doping Optimization

机译:通过基板掺杂优化降低RTN幅度和单阱诱导铁电FINFET的变化

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In this paper, we investigate the impacts of single trap induced Random Telegraph Noise (RTN) on Ferroelectric FinFET (FE-FinFET) with P-type and N-type substrates respectively, compared to FinFET. The trap position dependent RTN amplitude (AIds/Ids) along the channel length and fin height directions are examined. For FE-FinFET and FinFET at Vgs - 0V, N-type substrate with smaller work function lowers the channel conduction band energy near the bottom of fin along the fin height direction. Therefore, the maximum electron current density occurs at the bottom of fin which becomes the most critical position introducing worst RTN amplitude for N-type substrate. However, for FE-FinFET and FinFET with P-type substrate, the worst RTN amplitude occurs at 0.5 fin height position. Therefore, along the fin height direction, the worst RTN amplitude occurs at different position for FE-FinFET/FinFET with N-type and Ptype substrates respectively. Our results show that FE-FinFET exhibits smaller RTN amplitude than FinFET due to its smaller trap induced threshold voltage shift (ΔVT). Besides, for both FEFinFET and FinFET, N-type substrate shows smaller RTN amplitude and RTN induced ΔVT variations than P-type substrate. In other words, RTN induced variations can be suppressed by substrate doping optimization for FE-FinFET and FinFET.
机译:在本文中,与FinFET相比,我们分别研究单个陷阱诱导的HICELETRIC FINFET(FE-FINFET)对铁电FINFET(FE-FINFET)的影响。陷阱位置相关的RTN振幅(AI ds /一世 ds )检查沟道长度和鳍高度方向。在v的FIFFET和FINFET gs - 0V,具有较小功函数的N型衬底可降低沿翅片高度方向翅片底部附近的通道导管能量。因此,在翅片的底部发生最大电子电流密度,其成为为n型衬底引入最差的RTN幅度的最关键位置。然而,对于具有p型衬底的FinFET和FinFET,最差的RTN振幅在0.5翅片高度位置发生。因此,沿着翅片高度方向,分别以N型和PTYPE基板的FE-FINFET / FINFET在不同位置发生最差的RTN振幅。我们的结果表明,由于其较小的陷阱感应阈值电压移位(ΔV,Fe-FinFET表现出比FinFET更小的RTN振幅(ΔV t )。此外,对于FEFINFET和FINFET,n型衬底显示较小的RTN幅度和RTN感应ΔV t 变化比p型衬底。换句话说,可以通过FIFFET和FINFET的衬底掺杂优化来抑制RTN诱导的变化。

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