Modelling Stuck-at Faults in Combinational Circuits with Generalized Stochastic Petri Nets

摘要

The increasing progression of semiconductors scaling process into nanometric dimensions gives rise to new challenges for circuit robustness estimation, as well as for identifying potential defective circuit blocks early in the design process. In this work, we present a Generalized Stochastic Petri Net circuit model which can simulate stuck-at fault behavior of combinational circuits in order to identify the impact of a stuck-at fault defective circuit block in the overall reliability of the circuit.