Extracting of High-Level Structural Representation from VLSI Circuit Description Using Tangled Logic Structures

摘要

This paper proposes a method of automatic VLSI circuit analysis. We propose pattern-free, technology independent method for extracting of functional blocks with irregular structure. On the first step, transistors are grouped by their structure. Groups with irregular structure are highly interconnected to each other. Detecting Tangled Logic Structures (TLS) with a GTL-depended linear ordering and genetic algorithm divides the circuit due to its functional structure and forms the gate-level VLSI circuit. High-level functional blocks in circuit description consist of gate-level cells groups, which are also highly interconnected. After TLS-blocks extracting, it is possible to describe their function. TLS-blocks are smaller, represent a cell of high-level circuit, and are thus more suitable for further functional circuit analysis than a gate-level VLSI circuit. The experimental data obtained as a result of the principle electrical circuits of different degree of connectivity analysis confirmed the effectiveness of the proposed method.