Analysis of 2T 1D memory cell with various active capacitors

摘要

In this paper two transistor DRAM cell forms with one diode have been designed and analyzed. Insertion of diode in the memory cell fulfils the requirements of a capacitor to get improvisation in memory read and write operation. Both nmos and pmos transistors are used to implement two types of storage capacitors i.e. gate and junction. Concerned cells are compared on the basis of their read access time, write access time, retention time and power dissipation. All design and simulation work has been performed on Tanner EDA tool.