In this paper, an 8-bit Baugh-Wooley two's complement multiplier based on Wallace tree architecture is designed and simulated. Baugh-Wooley multiplier is popular for multiplication of signed multiplicands in 2's complement data representation. Baugh-Wooley multiplier can be implemented based on different architectures, such as array architecture or Wallace tree architecture. The strategy of Wallace tree architecture is to combine the partial product bits at the earliest opportunity, which leads to the fastest possible design. Furthermore, carry-save adders (CS A) can be used to reduce the number of addition cycles as well as to make each cycle faster. In this work, both Baugh-Wooley multipliers based on array architecture and Wallace tree architecture were designed and simulated in PSPICE. PSPICE simulation results show that the Wallace tree architecture not only works faster, but also consumes less power than the conventional array structure.
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