Ultra-thin actives for embedded components: halfway between thin film technology and embedded Surface Mounted Device.

摘要

Among the electronic assembly techniques, the embedded technology allows new compact architectures with active and passive components integrated into internal layers of printed circuit boards (PCBs) [1]. Embedded components increase both integration density and performance of electronic boards in particular RF performances and electromagnetic compatibility (EMC). For more than a decade, thin film technology used for embedded passives is defined as one of the key trends in downsizing. In addition to the advantages mentioned previously, the reliability is significantly improved because of the absence of solder joint. If the embedding of thin film passives in PCBs is now well known, very few studies have been performed on active components [2]. In this study a similar approach is considered for actives and thin film passives: the active components are embedded into the PCB without any package and are thinned with a specific method to ensure the mechanical handling. Consequently the PCB substitutes the classic housing of actives [3]. Moreover a dedicated manufacturing process makes it possible to replace solder joints with copper vias. In order to assess the reliability of the assemblies, simulations based on Finite Element Method (FEM) are performed to study the thermo-mechanical behavior of such innovative embedded active components during its operating lifetime considering the manufacturing process conditions. Indeed for the first time manufacturing stresses on assemblies are evaluated in a global multilayers PCB with bared and thinned embedded active components. The objectives of the present study are to determine a realistic assessment of the estimated lifetime of such assemblies with innovate embedded active components and to compare with classical actives. This study is carried out in the framework of a European project in collaboration with VALEO (automotive equipment supplier). Indeed, the requirements in reliability for VALEO are substantial which justifies the need for a predictive approach. In the medium term the aim is to make general design rules for actives and passives embedded in several layers of multilayered PCBs as part of a Design for Reliability (DFR).